Electronics
1. A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages

A. Mouri Zadeh Khaki; E. Farshidi

Articles in Press, Accepted Manuscript, Available Online from 30 April 2020

Abstract
  In this paper, a novel continuous-time 1-1 MASH ∆∑ Time-to-digital converter (TDC) is presented. Since the proposed design utilizes 12-bit quantizer based on Gated Switched-Ring Oscillator (GSRO) for both stages, it has been implemented all-digitally. By using a novel structure, only one multi-bit ...  Read More