N. S. Shahraki and S. H. Zahiri, “Low-Area/Low-Power CMOS Op-Amps design based on total optimality index using reinforcement learning approach,” Journal of Electrical and Computer Engineering Innovations, vol. 6, no. 2, pp. 193-208, 2018.
 M. Shaveisi and A. Rezaei, “Performance analysis of reversible sequential circuits based on carbon nanotube field effect transistors (CNTFETs),” Journal of Electrical and Computer Engineering Innovations, vol. 6, no. 2, pp. 167-178, 2018.
 W. Y. Choi and H. K. Lee, “Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs),” Nano convergence, vol. 3, no. 13, pp. 1-15, 2016.
 P. Jain, V. Prabhat, and B. Ghosh, “Dual metal-double gate tunnel field effect transistor with mono/hetero dielectric gate material,” Journal of Computational Electronics, vol. 14, no. 2, pp. 537-542, 2015.
 Y. Taur and E. J. Nowak, “CMOS devices below 0.1 /spl mu/m: how high will performance go?” in Proc. International Electron Devices Meeting. IEDM Technical Digest, pp. 215-218, 1997.
 R. Jhaveri, V. Nagavarapu, and J. C. Woo, “Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor,” IEEE Transactions on Electron Devices, vol. 58, no. 1, pp. 80-86, 2011.
 C.-M. Kyung, Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, Springer, 2015.
 J. K. Mamidala, R. Vishnoi, and P. Pandey, Tunnel Field-Effect Transistors (TFET): Modelling and Simulation, John Wiley & Sons, 2016.
 K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q,” in Proc. Digest. International Electron Devices Meeting, pp. 289-292, 2002.
 H. Kam, D. T. Lee, R. T. Howe, and T.-J. King, “A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics,” in Proc. IEEE International Electron Devices Meeting, pp. 463-466, 2005.
 G. Zhou, Y. Lu, R. Li, Q. Zhang, W. S. Hwang, Q. Liu, T. Vasen. C. Chen, H. Zhu, J.M Kuo, S. Koswatta, T. Kosel, M. Wistey, P. Fay, A. Seabaugh, and H. Xing, “Vertical InGaAs/InP tunnel FETs with tunneling normal to the gate,” IEEE Electron Device Letters, vol. 32, no. 11, pp. 1516-1518, 2011.
 D. S. Yadav, D. Sharma, B. R. Raad, and V. Bajaj, “Dual workfunction hetero gate dielectric tunnel field-effect transistor performance analysis,” in Proc. International Conference on Advanced Communication Control and Computing Technologies (ICACCCT), pp. 26-29, 2016.
 W. Y. Choi and W. Lee, “Hetero-gate-dielectric tunneling field-effect transistors,” IEEE Transactions on Electron Devices, vol. 57, no. 9, pp. 2317-2319, 2010.
 M. Shirazi and A. Hassanzadeh, “Design of a low voltage low power self-biased OTA using independent gate FinFET and PTM models,” AEU-International Journal of Electronics and Communications, vol. 82, pp. 136-144, 2017.
 A. Es-Sakhi and M. Chowdhury, “Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET,” Microelectronics Journal, vol. 62, pp. 30-37, 2017.
N. B. Bousari, M. K. Anvarifard, and S. Haji-Nasiri, “Improving the Electrical Characteristics of Nanoscale Triple-Gate Junctionless FinFET Using Gate Oxide Engineering,” AEU-International Journal of Electronics and Communications, vol. 108, pp. 226-234, 2019.
 Q. Zhang, W. Zhao, and A. Seabaugh, “Low-subthreshold-swing tunnel transistors” IEEE Electron Device Letters, vol. 27, pp. 297-300, 2006.
 W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Letters, vol. 28, pp. 743-745, 2007.
 F. Balestra, “Tunnel FETs for ultra low power nanoscale devices,” Available on: https://www.openscience.fr/IMG/pdf/iste_componano18v1n7.pdf, 2018.
 J. Cao, J. Park, F. Triozon, M. G. Pala, and A. Cresti, “Simulation of 2D material-based tunnel field-effect transistors: planar vs. vertical architectures,” Available on: https://www.openscience.fr/IMG/pdf/iste_componano18v1n4.pdf, 2018.
 U. E. Avci, R. Rios, K. Kuhn, and I. A. Young, “Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic,” in Proc. Symposium on VLSI Technology - Digest of Technical Papers, pp. 124-125, 2011.
 Y. Lv, W. Qin, C. Wang, L. Liao, and X. Liu, “Recent advances in low-dimensional heterojunction-based tunnel field effect transistors,” Advanced Electronic Materials, vol. 5, p. 1-15, 2019.
 R. N. Sajjad, U. Radhakrishna, and D. A. Antoniadis, "A tunnel FET compact model including non-idealities with verilog implementation,” Solid-State Electronics, vol. 150, pp. 16-22, 2018.
 A. Shaker, M. El Sabbagh, and M. M. El-Banna, “Influence of drain doping engineering on the ambipolar conduction and high-frequency performance of TFETs,” IEEE Transactions on Electron Devices, vol. 64, pp. 3541-3547, 2017.
 S. Garg and S. Saurabh, “Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis,” Superlattices and Microstructures, vol. 113, pp. 261-270, 2018.
 K. Boucart and A. M. Ionescu, “Length scaling of the double gate tunnel FET with a high-k gate dielectric,” Solid-State Electronics, vol. 51, no. 11, pp. 1500-1507, 2007.
 J. Knoch, S. Mantl, and J. Appenzeller, “Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices,” Solid-State Electronics, vol. 51, no. 4, pp. 572-578, 2007.
 S. Garg and S. Saurabh, “Improving the scalability of SOI-Based tunnel FETs using ground plane in buried oxide,” IEEE Journal of the Electron Devices Society, vol. 7, pp. 435-443, 2019.
 J.-S. Jang and W.-Y. Choi, “Ambipolarity factor of tunneling field-effect transistors (TFETs),” JSTS: Journal of Semiconductor Technology and Science, vol. 11, no. 4, pp. 272-277, 2011.
 T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-Gate strained-ge heterostructure tunneling FET (TFET) with record high drive currents and ≪60mV/dec subthreshold slope,” in Proc. IEEE International Electron Devices Meeting, pp. 1-3, 2008.
 N. Dagtekin and A. M. Ionescu, “Impact of super-linear onset, off-region due to uni-directional conductance and dominant cgd on performance of TFET-based circuits,” IEEE Journal of the Electron Devices Society, vol. 3, no. 3, pp. 233-239, 2014.
 “International Technology Roadmap for Semiconductors 2.0”, Available on: https://www.semiconductors.org/wp-content/uploads/2018/06/0_ 2015- ITRS- 2.0- Executive-Report-1.pdf, 2015.
 S. Saurabh and M. J. Kumar, “Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: Theoretical investigation and analysis,” Japanese Journal of Applied Physics, vol. 48, no. 6, pp. 1-7, 2009.
 D. B. Abdi and M. J. Kumar, “In-built N+ pocket pnpn tunnel field-effect transistor,” IEEE Electron Device Letters, vol. 35, no. 12, pp. 1170-1172, 2014.
 M. Karbalaei and D. Dideban, “A novel silicon on insulator MOSFET with an embedded heat pass path and source side channel doping,” Superlattices and Microstructures, vol. 90, pp. 53-67, 2016.
 D. S. Atlas, Atlas user’s manual. Silvaco International Software, Santa Clara, CA, USA, 2016.
 C. Anghel, A. Gupta, A. Amara, and A. Vladimirescu, “30-nm tunnel FET with improved performance and reduced ambipolar current,” IEEE Transactions on Electron Devices, vol. 58, no. 6, pp. 1649-1654, 2011.
 Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices: Cambridge university press, 2013.
 J.-P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI: Materials to VLSI, Springer Science & Business Media, 2004.
 H. L. Skriver and N. Rosengaard, “Surface energy and work function of elemental metals,” Physical Review B, vol. 46, no. 11, pp. 7157-7168, 1992.
 B. Dorostkar and S. Marjani, “DC analysis of pnpn tunneling field-effect transistor based on In0.35Ga0.65As,” HOLOS, vol. 1, pp. 288-296, 2018.
 H. Nam, M. H. Cho, and C. Shin, “Symmetric tunnel field-effect transistor (S-TFET),” Current Applied Physics, vol. 15, no. 2, pp. 71-77, 2015.
 K. M. Choi and W. Y. Choi, “Work-function variation effects of tunneling field-effect transistors (TFETs),” IEEE Electron Device Letters, vol. 34, no. 8, pp. 942-944, 2013.