Document Type: Original Research Paper


Department of Electrical Engineering, Mahshahr Branch, Islamic Azad University, Mahshahr, Iran



Background and Objectives: In recent decades, due to the effect of the short channel, the use of CMOS transistors in the nanoscale has become a major concern. One option to deal with this issue is the use of nano-transistors.
Methods: Using nano-transistors and multi-valued logic (MVL) can reduce the level of chips and connections and have a direct impact on power consumption. The present study reports the design of a new method of Multiplexers (MUXs) based on quaternary logic and transistors of carbon nanotubes (CNTFET) and having a new look at the layout and use of MUXs.
Results:The use of special rotary functions and unary operators in Quaternary logic in the design of MUXs reduced the number of CNTFETs from 27% to 54%. Also, the use of MUXs in the Adder structure resulted in a 54% reduction in Power Delay Product (PDP) and a 17.5% to 85.6% reduction in CNTFET counts.
Conclusion: The simulated results display a significant improvement in the fabrication of Adders, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits were evaluated under various operating conditions. The results show the stability of the proposed circuits.


Main Subjects

[1] S. Iijima, "Helical microtubules of graphitic carbon," Nature, 354(6348):  56-58, 1991.

[2] G. E. Moore, "Cramming more components onto integrated circuits,” IEEE Solid-State Circuits Society Newsletter, vol. 11(3): 33-35, 2006.

[3]J. Guo, S. O. Koswatta, N. Neophytou, M. Lundstrom, "Carbon nanotube field-effect transistors," International Journal of high-speed electronics and systems, 16,(4): 897-912, 2006.

[4] T. Temel, A. Morgul, "Implementation of multi-valued logic gates using full current-mode CMOS circuits," Analog Integrated Circuits and Signal Processing, 39(2): 191-204, 2004.

[5] A. N. Gupte,  A. K. Goel, "Study of quaternary logic versus binary logic," in Proc. First Great Lakes Symposium on VLSI, 1991.

[6] F. Sharifi, M. H. Moaiyeri, K. Navi, "A novel quaternary full adder cell based on nanotechnology," International Journal of Modern Education and Computer Science, 7(3): 19, 2015.

[7] E. Abiri, A. Darabi, S. Salem, "Design of multiple-valued logic gates using gate-diffusion input for image processing applications," Computers & Electrical Engineering, 69: 142-157, 2018.

[8] D. Das, A. Banerjee, V. Prasad, "Design of ternary logic circuits using CNTFET," in Proc. 2018 International Symposium on Devices, Circuits and Systems (ISDCS), 2018: IEEE, pp. 1-6.

[9] K. Vasundara Patel, K. Gurumurthy, "Design of high-performance quaternary adders," International Journal of Computer Theory and Engineering, 2(6): 944-952, 2010.

[10] C. Vudadha, A. Surya, S. Agrawal, M. Srinivas, "Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers," IEEE Transactions on Circuits and Systems I: Regular Papers, 65(12):  4313-4325, 2018.

[11] S. Lin, Y.B.  Kim, F. Lombardi, “CNTFET-based design of ternary logic gates and arithmetic circuits,” IEEE transactions on nanotechnology, 10(2): 217-225, 2009.

[12] S. A. Ebrahimi, M. R. Reshadinezhad, A. Bohlooli, M. Shahsavari, "Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits," Microelectronics Journal, 53: 156-166,  2016.

[13] F. Sharifi, M. H. Moaiyeri, K. Navi, N. Bagherzadeh, "Quaternary full adder cells based on carbon nanotube FETs," Journal of Computational Electronics, 14(3): 762-772, 2015.

[14] E. Roosta, S. A. Hosseini, "A Novel Multiplexer-Based Quaternary Full Adder in Nanoelectronics," Circuits, Systems, and Signal Processing, 38(9): 4056-4078, 2019.

[15] B. Srinivasu, K. Sridharan, "Carbon nanotube FET-based low-delay and low-power multi-digit adder designs," IET Circuits, Devices & Systems, 11(4): 352-364, 2016.

[16] M. H. Moaiyeri, M. Nasiri, N. Khastoo, "An efficient ternary serial adder based on carbon nanotube FETs," Engineering Science and Technology, an International Journal, 19(1): 271-278, 2016.

[17] M. H. Moaiyeri, K. Navi, O. Hashemipour, "Design and evaluation of CNFET-based quaternary circuits," Circuits, Systems, and Signal Processing, 31(5): 1631-1652, 2012.

[18]J. Deng and H.-S. P. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region," IEEE Transactions on Electron Devices, 54(12):  3186-3194, 2007.

 [19] A. Daraei, S.A. Hosseini, Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics, AEU Int. J. Electron. Commun. 105: 145–162, 2019.

[20] S. Fakhari, N. Hajizadeh Bastani , M.H. Moaiyeri, “A low-power and area-efficient quaternary adder based on CNTFET switching logic”, Analog Integrated Circuits and Signal Processing, 98(1): 221-232, 2019

[21]J. Deng, "Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45 nm node and carbon nanotube field-effect transistors," Stanford University, 2007.