Document Type: Original Research Paper


1 Graduate School of Electrical Engineering,Qazvin Islamic Azad University(QIAU), Qazvin, Iran

2 Department of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, Iran

3 Department of Computer and Electrical Engineering, Islamic Azad University (MIAU)


In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Therefore, operating frequency of the whole system isimproved which canbe mentioned as notable advantage of the proposed DLL. To obtain more accurate phases at the output signal, a new delay cell is introduced which is controlled by a single voltage. This control voltage, through equalizing the rise and fall time, regulate duty cycle of output clock. These features along with simplicity and low power consumption qualify the proposed architecture to be widely used in high speed systems. For better realization of the designed circuit’s behavior, simulation results are presented based on TSMC 0.35µm CMOS technology and 3.3-V power supply for a type II filter which demonstrate accuracy and perfect performance of this work.


[1] C-K. K Yang, “Delay-Locked Loops - An Overview” from “Phase Locking in High Performance Systems,” IEEE Press, 2003.

[2] M.-J. E. Lee, et al., “Jitter Transfer Characteristics of DelayLocked Loops Theories and Design Techniques,” IEEE J. SolidState Circuits, vol. 38, pp. 614-621, Apr. 2003.

[3] J. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996..

[4] A. Chandrakasan, W. J. Bowhill, and F. Fox, “Design of HighPerformance Microprocessor Circuit,” New York, IEEE Press, 2001.

[5] Giovanni Bianchi, “Phase-Locked Loop Synthesizer Simulation,” McGraw-Hill Electronic Engineering, 2005.

[6] R. E. Best, “Phase-Locked Loops: Design, Simulation, and Applications,” McGraw-Hill, 2003.

[7] M. Mansuri, D. Liu and C.-K. K. Yang, “Fast Frequency Acquisition Phase-Frequency Detectors for GSamples/s PhaseLocked Loops,” IEEE J. Solid-State Circuits, vol. 37, pp. 1331- 1334, Oct. 2002..

[8] H. Notani, H. Kondoh, and Y. Matsuda, “A 622-MHz CMOS PhaseLocked Loop with Precharge-Type Phase Frequency Detector,” VLSI Symp. Dig. Tech. Papers, June 1994, pp. 129-130.

[9] F. M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Transactions on Communications,” COM-28, No. 11, pp. 1849- 1858, November 1980.

[10] W. Rhee, “Design of High Performance CMOS Charge Pumps in Phase-Locked Loops,” Proc. IEEE Intl. Symp. On Circuits and Systems, vol. 1, 1999, pp. 545-548.

[11] B. Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill, New York, NY, 2001.

[12] Chen, Wu-Hsin, Maciej E. Inerowicz, and Byunghoo Jung. "Phase Frequency Detector with Minimal Blind Zone for Fast Frequency Acquisition," IEEE Transactions on Circuits and Systems II Express Briefs, 2010.

[13] Raghav, Himadri Singh, SachinMaheshwari, MolaSrinivasarao, and B. P. Singh. "Design of low power, low jitter DLL tested at all five corners to avoid false locking," 2012 10th IEEE International Conference on Semiconductor Electronics (ICSE), 2012.

[14] Chu Peng. "A novel Digital DLL and its implement on the FPGA.," International MultiConference of Engineers & Computer Scientists 2007 (Volume 1), 20070101.

[15] Jia Chen,''A delay lock loop for multiple clock phase/delays generation',' PHD thesis, Georgian statute of technology, 2005.

[16] Chih-Kong Ken Yang, ''an over view on Delay lock loops (DLLs),'' University of California, 2000.