Document Type: Original Research Paper


Department of Electrical Engineering, University of Guilan, Rasht, Iran


Due to the expected increase of defects in circuits based on deep submicron technologies, reliability has become an important design criterion. Although different approaches have been developed to estimate reliability in digital circuits and some measuring concepts have been separately presented to reveal the quality of analog circuit reliability in the literature, there is a gap to estimate reliability when circuit includes analog and digital structures. In this paper, we propose a new classification method using Monte Carlo analysis to calculate the reliability of analog circuits and show its efficacy when it is used for a combination of analog and digital circuits. Our method is based on signal reliability concepts and measures the probability of passing correct or faulty values. Furthermore, we compare our reliability measurements with the reliability definitions come from other failure mechanisms in sub-micron technologies. Simulation results show the reliability measurement presented here which provides key information for reliability improvement and monitoring.

Graphical Abstract


[1] D. T. Franco, M. C. Vasconcelos, L. Navine, and J. F. Naviner, “Signal probability for reliability evaluation of logic circuits,” Microelectronics Reliability, vol. 48, pp. 1586-1591. 2008, DOI: 10.1016/j.microrel. 2008.07.002

[2] Y. Chen, C. Ye, X. Zhang, and R. Kang, D. Xue, “Reliability modeling method of electronic products considering failure mechanism dependence,” IEEE 4th Annual International Conference on Cyber Technology in Automation, Control, and Intelligent Systems, pp. 419-423, 2014. DOI: 10.1109/CYBER.2014.6917500

[3] L. A. de B. Naviner, J. F. Naviner, T. Ban, and G.S. junior, “Reliability analysis based on significance,” Institut TELECOMParisTech, LTCI-CNRS, pp. 1-7. 2011.

[4] Panasonic: Fauilure Mechanism of Semiconductor Devices, Japan (2009).

[5] A. Birolini, “Reliability engineering,” (3rd eds.), Springer, Heidelberg. pp. 4-7. 1999. DOI: 10.1007/978-3-662-03792-8.

[6] A. T. de Almeida, C. A. V. Cavalcanteí, M. H. Alencar, R. J. P. Ferreira, and T. V. Garcez, “Multicriteria and Multiobjective Models for Risk Reliability and Maintenance Decision Analysis,” Springer. Switzerland, pp. 115-121, 2015. DOI: 10.1007/978-3-319-17969-8

[7] A. Balasinski, “Semiconductors integrated circuit design for manufacturability,” Taylor & Francis Group, London, 2012. [8] G. Groeseneken, R. Degraeve, T. Nigam, G. Van den bosch, and H. E. Maes, “Hot carrier degradation and time-dependent dielectric breakdown in oxides,” Microelectronic Engineering, 49, pp. 27-40. 1999. DOI: 10.1016/S0167-9317(99)00427-X.

[9] J. R. Black, “Electro migration-A Brief Survey and Some Recent Results,” IEEE Transactions on Electron Devices, 16 (4), pp. 338-347. 1969. DOI: 10.1109/TED. 1969.16754.

[10] J. Kumar, M. B. Tahoori, “A low power soft error suppression technique for dynamic logic,” 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 454-462, 2005. DOI:10.1109/ DFTVS.2005.9.

[11] J. M. Rabaey, A. Chandrakasan, B. Nikolic, “Digital integrated circuits. A design perspective,” (2nd eds.) Prentice Hall. pp. 331-338, 2003.

[12] Y. Sasaki, K. Namba, H. Ito, “Circuit and latch capable of masking soft errors with Schmitt trigger,” Springer Electronic Testing journal, 24 (1-3), pp. 11–19. 2008. DOI: 10.1007/s10836-007-5034-2

[13] D. T. Franco, M. C. Vasconcelos, L. Naviner, J. F. Naviner, “Reliability of logic circuits under multiple simultaneous faults,” in 51st Midwest Symposium on Circuits and Systems, pp. 265–268, 2008. DOI: 10.1109/ MWSCAS.2008.4616787 [14] ISCAS85 Benchmark Circuits Information [Online]. 2011.

[15] H. Cha, J. H. Patel, “A logic level model for -partical hits in cmos circuits," pp. 538-542. 1993. DOI: 10.1109/ICCD.1993.393319

[16] V. A. Carreno, G. Chio, K.R. lyer, “Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system,” In NASA Tech Memorandum 4241. pp. 1 – 20. 1990. Biographies