A new low power high reliability flip-flop robust against process variations

Document Type: Research Paper

Authors

Department of Electrical Engineering, University of Guilan, Rasht, Iran.

Abstract

Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In this paper we combined these two generally separate addressed issues to reach a new low power high reliability flip-flop (LP-HRFF). LP-HRFF operates over 1GHz clock frequency and structured based on an appropriate combination of dual interlocked storage cell, level converting techniques and clock signal controlled gates. The extensive simulations exhibit LP-HRFF has 0% single event upset rate against single transient events occurred on inputs and internal nodes and show the improvement of power consumption up to 42.8% and power delay product up to 24.6% when compared with its counterparts. Furthermore, the simulation results approve the robustness and efficiency of the proposed flip-flop against process variations.

Graphical Abstract

A new low power high reliability flip-flop robust against process variations

Keywords


[1] G. F. Ziegler and W. A. Lanford, “The effect of sea level cosmic rays on electronic devices,” in proc. 1980 International SolidState Circuits Conf., San Francisco, CA, USA, pp. 70 – 71, 1980.

[2] Y. Lin, M. Zwolinski, and B. Halak, “A low cost radiation hardened flip-flop,” in proc. 2014 Design Automation and Test in Europe Conf., Dresden, Germany pp. 1-6, 2014.

[3] M. Masuda, K. Kubota, R. Yamamoto, J. Furuta, K. Kobayashi, and H. Onodera, “A 65nm low power adaptive coupling redundant flip-flop,” IEEE Trans. Nuclear Science, vol. 60, pp. 2750-2755, 2013.

[4] S. M. Jahinuzzaman and R. Islam, “Tspc-DICE: A single phase clock high performance SEU hardened flip-flop,” in proc. 2010 Circuits and Systems. IEEE International Midwest Symposium., pp. 73-76.

[5] R. Islam, “A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop,” in proc. IEEE 13th International Symposium on Quality Electronic Design., Santa Clara, CA, USA pp. 347-352, 2012.

[6] K. T. Chen, T. Fujita, H. Hara, and M. Hamada, “A 77% energy saving 22 transistor single phase clocking D flip- flop with adaptive coupling configuration in 40nm CMOS,” in proc. 2011 Solid-State Circuits Conf Digest of Technical Papers., San Francisco, CA, USA , pp. 338-340, 2011.

[7] J. Fa lin, “Low power pulse triggered flip flop design based and signal feed through scheme,” IEEE Trans. Very Large Scale Integration Systems, vol. 18, pp. 181-185, 2013.

[8] N. K. Saini and K. Kashyap, “Low power dual edge triggered flip flop,” in proc. 2014 IEEE International Conf Signal Propagation and Computer technology, Ajmer, India , pp. 125-128, 2014.

[9] J. Shen, L. Geng, G. Xiang, and J. Liang, “Low power level converting flip flop with a conditional clock technique in dual supply systems,” Microelectronics journal, vol. 45, pp. 857-863, 2014.

[10] R. Islaml, S. E. Esmaeilil, and T. Islam, “A high performance clock precharge SEU hardened flip-flop,” in proc. 2011 IEEE International Conf on ASIC, Xiamen, China, pp. 574-577, 2011.

[11] R. Islam, “High-speed energy-efficient soft error tolerant flipflops,” M.Sc. Dissertation, Concordia, University Montreal, Quebec, Canada, 2011.

[12] http://ptm.asu.edu.

[13] H. Cha and J. H. Patel, “A logic level model for -particle hits in CMOS circuits,” in Proc. 1993 IEEE International Conf on VLSI., pp. 538-542, 1993.

[14] V. Carreno and G. Chio, “Analog-digital simulation of transientinduced logic errors and upset susceptibility of an advanced control system,” in proc. 1990, NASA Tech Memorandum 4241, NASA; United States, pp. 1-20, 1990.

[15] H. Hung and V. Adzic, “Monte carlo simulation of device variations and mismatch in analog integrated circuits,” in Proc. 2006 National Conf on under Graduate Research, North Carolina, USA, pp. 1-8, 2006.

[16] N. H. E. Weste and D. M. Harris, CMOS VLSI Design A Circuits and Systems Perspective, New York: Wiley, 2009, p. 838.