A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology

Document Type: Research Paper

Author

Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran

Abstract

A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneously as well. It is noteworthy that, exerting the suggested method the total capacitance and the ratio of the MSB and LSB capacitor are decreased, as a result, the speed and accuracy of the ADC are increased reliably. Therefore, applying the proposed idea, it is reliable that to attain a 12-bit resolution ADC at 76MS/s sampling rate. Furthermore, the power consumption of the proposed ADC is 694µW with the power supply of 1.8 volts correspondingly. The proposed post-layout SAR ADC structure is simulated in all process corner condition and different temperatures of -50℃ to +50℃, and performed using the HSPICE BSIM3 model of a 0.18µm CMOS technology.

Graphical Abstract

A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology

Keywords


[1]     S. Liu, Y. Shen, and Z. Zhu, “A 12-bit 10 MS/s SAR ADC with high linearity and energy-efficient switching,” IEEE Transactions on Circuits and Systems, vol. 63, no. 10, pp. 1616 – 1627, 2016.

[2]     C. Liu, M. Huang, and Y. H. Tu, “A 12 bit 100 MS/s SAR-assisted digital-slope ADC,” IEEE Journal of Solid-State Circuits,  vol. 51, no. 12, pp. 2941-2950, 2016.

[3]   Kh. Hadidi, “Data converter course notes,” Urmia University, Urmia, Iran, 2005.

[4]     Y. Chung, M. Wu, and H. Li, “A 12-bit 8.47-fJ/conversion-step capacitor-swapping SAR ADC in 110-nm CMOS,” IEEE Transactions on Circuits and Systems, vol. 62, no. 1, pp. 10-18, 2015.

[5]     Y. Chung, M. Wu, and H. Li, “A 14b 80 MS/s SAR ADC with 73.6 dB SNDR in 65 nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3059-3066, 2013.

[6]     Y. Song, Z. Xue, Y. Shiquan Fan, and L. Geng, “A 0.6-V 10-bit 200-kS/s fully differential SAR ADC with incremental converting algorithm for energy efficient applications,” IEEE Transactions on Circuits and System, vol. 63, no. 4, pp. 449-458, 2016.

[7]     Y. Tao and Y. Lian, “A 0.8-V, 1-MS/s, 10-bit SAR ADC for multi-channel neural recording,” IEEE Transactions on Circuits and Systems, vol. 62, no. 2, pp. 366-375, 2015.

[8]     S. Lei, D. Qinyuan, L. Chuangchuan, and Q. Gaoshuai, “Analysis on capacitor mismatch and parasitic capacitors effect of improved segmented-capacitor array in SAR ADC,” in Proc. Third International Symposium on Intelligent Information Technology Application, vol. 2, pp. 280-283, Shanghai, China, 2009.

[9]     J. Wen, P. Hung Chang, J. Huang, and W. Lai, “Chip design of a 12-bit 5MS/s fully differential SAR ADC with resistor- capacitor array DAC technique for wireless application,” in Proc. IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC), pp. 1-4, Ningbo, China, 2015.

 [10] W. Lai, J. Huang, C. Hsieh, and F. Kao, “An 8-bit 2 MS/s successive approximation register analog-to-digital converter for bioinformatics and computational biology Application,” IEEE 12th International Conference on Networking, Sensing and Control (ICNSC), pp. 576-579, Taipei, Taiwan, 2015.

[11]  W. Lai J. Huang,  T. Ye, and C.W. Shih “Integrated successive approximation register analog-to-digital converter for healthcare systems applications,” in Proc. 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-3, Guilin, China, 2014.

[12]  W. Lai, J. Huang, and W. Lin “1MS/s low power successive approximations register ADC for 67-fJ/conversion-step,” in Proc. 2012 IEEE Asia Pacific Conference on Circuits and Systems,  pp. 260-263, Kaohsiung, Taiwan, 2012.

[13]  P. Lee, J. Lin, and C. Hsieh, “A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with input-range-adaptive switching,” IEEE Transactions on Circuits and Systems, vol. 63, no. 12, pp. 2149-2157, 2016.

[14]  M. Kim, Y. Kim, Y. Kwak, and G. Ahn, “A 12-bit 200-kS/s SAR ADC with hybrid RC DAC,” in Proc. 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 185-188, Ishigaki, Japan, 2014.

[15]  S. Wong, U. Chio, Y. Zhu, S. Sin, S. Pan U, and R. Paulo Martins, “A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC,” IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1783-1794, 2014.

[16]  M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto “A 10-b 50-MS/s 820µW SAR ADC with on-chip digital calibration,” IEEE Transactions on Biomedical Circuits and Systems, vol. 4, no. 6, pp. 410-416, 2010.

 [17] Y. Chung, C. Yen, and M. Hsuan Wu, “A 24µW 12-bit 1-MS/s SAR ADC with two-step decision DAC switching in 110-nm CMOS,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 11, pp. 3334-3344, 2016.

 [18] M. Yee Ng, “0.18um low voltage 12-bit successive-approximation-register analog-to-digital converter (SAR ADC),” in Proc. 3rd Asia Symposium on Quality Electronic Design (ASQED), pp. 277-281, Kuala Lumpur, Malaysia, 2011.

[19]  W. Tseng, W. Lee, C. Huang, and P. Chiu, “A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters,” IEEE Journal of Solid-State Circuits, vol. 51, no. 10, pp. 2222- 2231, 2016.

 [20] S. Kazeminia and S. Mahdavi, “A 800MS/s, 150µV input-referred offset single-stage latched comparator,” in Proc. 23rd International Conference Mixed Design of Integrated Circuits and Systems, pp. 119-123, Lodz, Poland, 2016.

[21]  S. Kazeminia, S. Mahdavi, and R. Gholamnejad, “Bulk controlled offset cancellation mechanism for single-stage latched comparator,” in Proc. 23rd International Conference Mixed Design of Integrated Circuits and Systems, pp. 174-178, Lodz, Poland, 2016.

[22]  W. Xiong, Y. Guo, U. Zschieschang, H. Klauk, and B. Murmann, “A 3-V, 6-bit C-2C digital-to-analog converter using complementary organic thin-film transistors on glass,” IEEE Journal of Solid-State Circuits, vol. 45, no. 7, pp. 1380-1388, 2010.

[23] Kh. Hadidi, V. S. Tso, and G. C. Temes, “An 8-b 1.3-MHz successive approximation  A/D Converter,” IEEE J. Solid-State Circuits, vol. 25, no. 3, pp. 880-885, June 1990.

[24] L. Cong, “Pseudo C-2C ladder-based data converter technique,” IEEE Trans. Circuits Syst. II, Analog Digital Signal Processing, vol. 48, no. 10, pp. 927-929, 2001.

[25] Y. M. Liao and T. C. Lee, “A 6-b 1.3Gs/s A/D converter with C-2C switch-capacitor technique,” in Proc. IEEE Int. Symp. on VLSI-DAT, pp. 1-4. Hsinchu, Taiwan, 2006.

[26] H. Kim, Y. Min, Y. Kim, and S. Kim, “A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array,” in Proc. IEEE Int. Conf. on EDSSC, pp. 1-4, Hong Kong, China, 2009.

 [27] S. Kazeminia, S. Mahdavi, and Kh. Hadidi, “Digitally-assisted offset cancellation technique for open loop residue amplifiers in high-resolution and high-speed ADCs,” in Proc. 23rd International Conference Mixed Design of Integrated Circuits and Systems, pp. 197-202, Lodz, Poland, 2016.

[28] D. S. Khosrov, “A new offset cancelled latch comparator for high-speed, low-power ADCs,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems, APCCAS, pp. 13-16,  Kuala Lumpur, Malaysia, Dec., 2010.

 [29] S. W. Lee, H. J. Chung, and C.-H. Han, “C-2C digital-to-analogue converter on insulator,” IEEE Electron. Lett., vol. 35, no. 15, pp. 1242-1243, 1999.

 

 

How to cite this paper:

S. Mahdavi, “A 12 bit 76MS/s SAR ADC with a capacitor merged technique in 0.18µm CMOS technology,” Journal of Electrical and Computer Engineering Innovations, vol. 5, no. 2, pp. 121-130, 2017.

URL: http://jecei.sru.ac.ir/article_693.html

 
 

 

 

 

 

 

 

 

 

 

 

 

[30]  M. Taherzadeh-Sani, R. Lotfi, and F. Nabki, “A 10-bit 110 kS/s 1.16 muhbox {W} SA-ADC with a hybrid differential/single-ended DAC in 180-nm CMOS for multichannel biomedical applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 8, pp. 584-588, 2014.

 [31] W. Lai, J. Huang, and C. Hsieh, “A 10-bit 20 MS/s successive approximation register analog-to-digital converter using single-sided DAC switching method for control application,” in Proc. CACS International Automatic Control Conference (CACS 2014), pp. 29-33, Kaohsiung, Taiwan, 2014.

 [32] S. Aghaie, J. Mueller, R. Wunderlich, and S. Heinen, “Design of a low-power calibrate-able charge-redistribution SAR ADC”, 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 1-4 Grenoble, France, 2014.

 [33] R. Rajendran, P.V. Ramakrishna, “A design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS process”, in Proc. International Symposium on Electronic System Design (ISED),  pp. 23-27, Kolkata, India, 2012.

[34] S. P. Singh, A. Prabhakar, and A. B. Bhattcharyya, “C-2C ladder-based D/A converters for PCM codecs,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp.1197-1200, 1987.