Wind Turbine
M. Kamarzarrin; M.H. Refan; P. Amiri; A. Dameshghi
Abstract
Background and Objectives: Renewable energy, like wind turbines, is growing rapidly in the world today due to environmental pollution, so their maintenance plans are very important. Fault diagnosis and fault-tolerant approaches are typical methods to reduce the cost of energy production and downtime ...
Read More
Background and Objectives: Renewable energy, like wind turbines, is growing rapidly in the world today due to environmental pollution, so their maintenance plans are very important. Fault diagnosis and fault-tolerant approaches are typical methods to reduce the cost of energy production and downtime of Wind Turbines (WTs). Methods: In this paper, a new Hardware In the Loop (HIL) simulator based on Double Feed Induction Generator (DFIG) for fault diagnosis and fault-tolerant control is proposed. The system developed as a laboratory bed uses a generator with a power of about 90 kW, which is connected from two sides to a back-to-back power converter with a power of one-third of the generator power. The generator is connected to a motor as a propulsion and wind energy replacement with a power of about 110 kW, and this connection is established through a gearbox with a gear ratio of more than three. Results: The effectiveness of the proposed simulator is evaluated based on different fault representations back-to-back converter and generator.Conclusion: The experiment shows that the Condition Based Maintenance (CBM) is improved by the proposed simulator and the fault is modeled before serious damage occurs. This setup is effective for the development of wind turbine fault analysis software. As the testing on real WTs is very expensive, to improve and develop the research fields of condition monitoring and WT control, this low-cost setup is effective.
Electronic Circuits
M. A. Latifzadeh; P. Amiri; H. Allahyari; H. Faezi
Abstract
Background and Objectives: Many applications use boost converters as front-end circuits, including power factor correction (PFC), solar power generation, fuel cell power conversion, battery chargers, and uninterruptible power supply. In addition, boost converters have a simple structure with low component ...
Read More
Background and Objectives: Many applications use boost converters as front-end circuits, including power factor correction (PFC), solar power generation, fuel cell power conversion, battery chargers, and uninterruptible power supply. In addition, boost converters have a simple structure with low component counts, which makes them a convenient choice.Methods: This article proposes a coupled-inductor active auxiliary circuit to create a new low-stress boost converter with soft-switching. The proposed auxiliary circuit supplies the main switch and diode with soft-switching ZVC turn-on and ZCS turn-off states. The main switch and diode are not deal with any extra stress of voltage or current. Furthermore, the soft switching condition is also provided for auxiliary circuit components.Results: The proposed auxiliary circuit also has a simple structure, low circulating current losses, low cost, and simplicity in control. The operation state and performance of the proposed soft-switching boost converter are examined, and the design procedure is presented. Finally, a 200W prototype is implemented and tested to validate the theoretical results. The offered experimental data verified the theoretical analysis.Conclusion: This paper provides a new low-stress soft-switching boost converter using a simple coupled-inductor in the auxiliary circuit. Moreover, the auxiliary part consists of two diodes, one switch, one resonance capacitor, and a coupled inductor. The suggested auxiliary circuit provides soft switching condition for the main switch, which provides ZVS in the turn-on transient and ZCS in the turn-off transient, while in this situation, the soft-switching condition is provided for the auxiliary switch, which turns on under ZCS and also turns off with practically ZVS conditions. The auxiliary circuit does not impose additional voltage or current stress on the main switch. A 200 W prototype is implemented to validate the performance of this snubber cell. The experimental data reported here support the theoretical analysis. The best point of efficiency is 95.9% which is occurred at maximum load, and is 6.3% greater than the traditional counterparts.
Power Divider
M. Mirzajani Darestani; M. Tavakoli; P. Amiri
Abstract
Background and Objectives: In this paper, a new design strategy was proposed in order to enhance bandwidth and efficiency of power amplifier.Methods: To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka band, i.e. the frequency ...
Read More
Background and Objectives: In this paper, a new design strategy was proposed in order to enhance bandwidth and efficiency of power amplifier.Methods: To realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka band, i.e. the frequency range of 26.5-40GHz. To design the power amplifier, first a power divider (PD) with a very wide bandwidth, i.e. 1-40GHz, was designed to cover the whole Ka band. The designed Doherty power amplifier consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade distributed power amplifier was used. The main reason for combining the distributed structure and cascade structure was to increase the gain and linearity of the power amplifier.Results: Measurements results for designed power divider are in good agreement with simulations results. The simulation results for the introduced structure of power amplifier indicated that the gain of proposed power amplifier at the frequency of 26-35GHz was more than 30dB. The diagram of return loss at the input and output of power amplifier in the whole Ka band was less than -8dB. The maximum Power Added Efficiency (PAE) of the designed power amplifier was 80%. The output p 1dB of the introduced structure was 36dB, and the output power of power amplifier was 36dBm. Finally, the IP3 value of power amplifier was about 17dB.Conclusion: The strategy presented in this paper is based on usage of Doherty and distributed structures and a new wideband power divider to benefit from their advantages simultaneously.
Electronics
F. Abdi; P. Amiri; M.H. Refan
Abstract
Background and Objectives: Adaptive algorithm adjusts the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor.Methods: Vedic mathematics ...
Read More
Background and Objectives: Adaptive algorithm adjusts the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor.Methods: Vedic mathematics is used to implement the multiplier and the divider operations in the VFF equations. The linear exponentially weighted recursive least squares as the main algorithm is implemented in many applications such as the adaptive controller, the system identification, active noise cancellation techniques, and etc. The DCD method calculates the inverse matrix in the ERLS algorithm and decreases the resources used in the field-programmable gate array, also the designer can use the cheaper FPGA board to implement the adaptive algorithm because the method doesn't need lots of resources.Results: The proposed method is implemented with ISE software on the Spartan 6 Xilinx board. The proposed algorithm calculates the multiplication result with less than 15ns time and reduces the used FPGA resources to lower than 20% as compared with the classic RLS.Conclusion: The proposed method decreases the area and increases the computation speed. Also, it leads to implementing complex algorithms with simple structures and high technology.
B. Shojaei Tabatabaei; P. Amiri
Abstract
This paper presents a design of an UWB downconversion integrated CMOS resistive ring mixer with Linear Voltage Regulator (LVR), to supply required biasing voltages for the mixer section. The designed mixer circuit has been optimized for using in heart rate extraction system with microwave Doppler radar ...
Read More
This paper presents a design of an UWB downconversion integrated CMOS resistive ring mixer with Linear Voltage Regulator (LVR), to supply required biasing voltages for the mixer section. The designed mixer circuit has been optimized for using in heart rate extraction system with microwave Doppler radar at 2.4GHz frequency. This mixer needs 2 DC bias voltages equal to 0.5 and 1 volts for its best operation. The designed LVR circuit would supply needed bias voltages. This mixer is called UWB and the changes in its necessary bias voltages would result in its weak operation. The design has been implemented in TSMC 0.18µm CMOS technology and simulated by Advanced Design System (ADS) software. Simulation results indicate good operation of regulator and mixer output during input changes.
