S. SamadiGorji; B. Zakeri; M.R. Zahabi
Abstract
The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer ...
Read More
The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. Based on this formula, the phase noise diagram as a function of bandwidth is plotted. From the analysis and simulation results, it is observed that the synthesizer has a minimum phase noise at a particular bandwidth.
