VLSI
Seyede Mahboobeh Mousavi Monazah; Nabiollah Shiri; Mahmood Rafiee; Ayoub Sadeghi
Abstract
Background and Objectives: In modern digital design, ternary logic gives simplicity and efficiency by reducing connectivity and chip area. This paper presents a new ternary decoder with only two ternary inverters and one binary NOR gate. One of the inverters is used simultaneously as a negative ternary ...
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Background and Objectives: In modern digital design, ternary logic gives simplicity and efficiency by reducing connectivity and chip area. This paper presents a new ternary decoder with only two ternary inverters and one binary NOR gate. One of the inverters is used simultaneously as a negative ternary inverter (NTI), and a positive ternary inverter (PTI) to attain circuit area reduction. Also, using the binary NOR instead of the ternary NOR eliminates don’t care states (middle voltage mode). The proposed decoder is implemented with complementary metal-oxide-semiconductor (CMOS), double pass logic (DPL), gate diffusion input (GDI), and pass transistor logic (PTL). In the proposed ternary decoder, the four mentioned technologies show an appropriate power delay product (PDP) and a smaller occupied area compared to the literature. Methods: In this paper, all simulations are performed using the 90 nm model, BSIM4 (level 54) version 4.4 by the HSPICE tool. The CMOS, DPL, PTL, and GDI techniques are used in the presented ternary decoder, and the results are extracted. The decoder shows good functionality compared to the previous research when implemented by these four circuits, but the best performance in terms of PDP results is from the CMOS.Results: The CMOS-based ternary decoder has only 10 transistors and shows the best results, its power consumption, and propagation delay are 25 μW and 0.07 ns, respectively. Besides, the number of transistors is reduced by 16.66% while it has 2 times increase in speed compared to the best decoders in previous research. The proposed high-speed and low-complexity decoder can be used in full adders (FAs) and digital signal processors (DSPs). Conclusion: Due to the application and advantage of ternary logic over binary, a ternary decoder with CMOS technique is designed that has fewer elements, a smaller area, and high speed compared to the existing ternary decoders. This new decoder includes only two ternary inverters and one binary NOR gate one of the inverters is used as a negative ternary inverter (NTI), and a positive ternary inverter (PTI), simultaneously. Also, the use of binary NOR gate eliminates don’t care states and reduces the circuit area.
Analogue Integrated Circuits
F. Shakibaee; A. Bijari; S.H. Zahiri
Abstract
Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). So, different structures have been proposed to improve their performance. Power, delay, offset, and noise are the important factors that have significantly affect ...
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Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). So, different structures have been proposed to improve their performance. Power, delay, offset, and noise are the important factors that have significantly affect the comparator’s performance. In low power applications, power consumption and delay are the critical concerns that should be minimized to obtain better performance. In this work, a low-power and high-speed comparator has been proposed, which is suitable for applications operating at a low power supply.Methods: Based on the conventional structure of the comparator, some modifications are implemented to achieve better performance in terms of power consumption and delay. Additionally, the proposed structure gives great performance when the difference of inputs is very small. To verify the proposed structure, it is designed and simulated in a 0.18 μm CMOS technology with a power supply of 1 V and sampling frequency of 2 MHz.Results: To draw a fair comparison, the conventional and proposed structure is simulated in equal circumstance. The size of transistors is designed with appropriate W/L ratios to achieve appropriate performance. The proposed structure not only reduces the power consumption by 44%, but also it decreases the delay by 9.1%. The power consumption of the proposed structure is around 0.12 µw. The total occupied area by the proposed structure is approximately 127.44 µm2.Conclusion: In this paper, we presented a delay analysis for the proposed dynamic comparator. Also, based on theoretical analyses, a new dynamic comparator consumes less power and operates faster compared with the conventional structure. The simulation results verify the theoretical analysis.
