Shahid Rajaee Teacher Training University Journal of Electrical and Computer Engineering Innovations (JECEI) 2322-3952 9 1 2020 11 18 Fast and Efficient Hardware Implementation of 2D Gabor Filter for a Biologically-Inspired Visual Processing Algorithm 93 102 1490 10.22061/jecei.2020.7548.404 EN A. Mohammadi Anbaran Electrical Engineering Department, Faculty of Engineering, Islamic Azad University, Science and Research Branch, Tehran, Iran. P. Torkzadeh Electrical Engineering Department, Faculty of Engineering, Islamic Azad University, Science and Research Branch, Tehran, Iran. R. Ebrahimpour Artificial Intelligence Department, Faculty of Computer Engineering, Shahid Rajaee Teacher Training University; Tehran, Iran. School of Cognitive Sciences, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran. N. Bagheri Communication Engineering Department, Faculty of Electrical Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran. Journal Article 2020 05 24 <strong>Background and Objectives:</strong> Programmable logic devices, such as Field Programmable Gate Arrays, are well-suited for implementing biologically-inspired visual processing algorithms and among those algorithms is HMAX model. This model mimics the feedforward path of object recognition in the visual cortex. <br /><strong>Methods:</strong> HMAX includes several layers and its most computation intensive stage could be the S1 layer which applies 64 2D Gabor filters with various scales and orientations on the input image. A Gabor filter is the product of a Gaussian window and a sinusoid function. Using the separability property in the Gabor filter in the 0° and 90° directions and assuming the isotropic filter in the 45° and 135° directions, a 2D Gabor filter converts to two more efficient 1D filters.<br /><strong>Results:</strong> The current paper presents a novel hardware architecture for the S1 layer of the HMAX model, in which a 1D Gabor filter is utilized twice to create a 2D filter. Using the even or odd symmetry properties in the Gabor filter coefficients reduce the required number of multipliers by about 50%. The normalization value in every input image location is also calculated simultaneously. The implementation of this architecture on the Xilinx Virtex-6 family shows a 2.83ms delay for a 128×128 pixel input image that is a 1.86X-speedup relative to the last best implementation.<br /><strong>Conclusion:</strong> In this study, a hardware architecture is proposed to realize the S1 layer of the HMAX model. Using the property of separability and symmetry in filter coefficients saves significant resources, especially in DSP48 blocks. https://jecei.sru.ac.ir/article_1490_0ae6cdc236e78f78edacd1d286bd19e1.pdf