Optoelectronics and Photonics
M. Shaveisi; A. Rezaei
Abstract
Background and Objectives: This study presents the importance of reversible logic in designing of high performance and low power consumption digital circuits. In our research, the various forms of sequential reversible circuits such as D, T, SR and JK flip-flops are investigated based on carbon nanotube ...
Read More
Background and Objectives: This study presents the importance of reversible logic in designing of high performance and low power consumption digital circuits. In our research, the various forms of sequential reversible circuits such as D, T, SR and JK flip-flops are investigated based on carbon nanotube field-effect transistors. Methods: By simultaneous using of the reversible logic gates and carbon nanotube transistors in implementation of various flip-flops and introducing suitable transistor circuits of conventional reversible gates, all reversible flip-flops are simulated in two voltages, 0.3 and 0.5 Volt. The Hspice_H-2013.03-SP2 software is used to simulate these circuits using the 32nm CNTFET technology (the standard Stanford spice model). Results: The simulation results indicate a significant reduction in the average power consumption of D, T, SR and JK flip-flops, respectively about 99.98%, 82.79%, 60.46%, and 81.53%. Conclusion: Our results show that the proposed structures have achieved a high performance in terms of average power consumption and PDP.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
S. Mahdavi
Abstract
A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneously ...
Read More
A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneously as well. It is noteworthy that, exerting the suggested method the total capacitance and the ratio of the MSB and LSB capacitor are decreased, as a result, the speed and accuracy of the ADC are increased reliably. Therefore, applying the proposed idea, it is reliable that to attain a 12-bit resolution ADC at 76MS/s sampling rate. Furthermore, the power consumption of the proposed ADC is 694µW with the power supply of 1.8 volts correspondingly. The proposed post-layout SAR ADC structure is simulated in all process corner condition and different temperatures of -50℃ to +50℃, and performed using the HSPICE BSIM3 model of a 0.18µm CMOS technology.
