Document Type: Original Research Paper


1 Dept. of Electrical Engineering, Faculty of Electrical and Computer Engineering, University of Birjand, Birjand, Iran

2 Department of Electrical Engineering, Faculty of Engineering, University of Birjand,

3 Department of Electrical Engineering, Faculty of Engineering, University of Birjand, Birjand, Iran


The most important very large scale integration (VLSI) circuits are digital filters and transformers, which are widely used in audio and video processing, medical signal processing, and telecommunication systems. High-level synthesis (HLS) is one of the substantial steps in designing VLSI digital circuits. The primary purpose of HLS is to minimize the digital units used in the system to improve their power, delay, and area. This is fulfilled by analyzing the data flow graph (DFG). The complex, expansive, and discrete nature of design space in high-level synthesis problems has made them one of the most difficult problems in VLSI circuit design. In the modified MFO algorithm presented in this paper, a hyperbolic spiral is chosen as the update mechanism of moths. Also, by presenting a new approach, a paramount issue involved in applying meta-heuristic methods for solving HLS problems of VLSI circuits has been disentangled. Finally, by comparing the performance of the proposed method with Genetic algorithm (GA)-based method and particle swarm optimization (PSO)-based method for the synthesis of the digital filters, it is concluded that the proposed method has the higher ability in the HLS of data path in digital filters. The best improvement is 2.78% for the delay (latency), 6.51% for the occupied area of the chip and 6.93% in power consumption. Another feature of the proposed method is its high-speed in finding optimal solutions, in a manner which, more than 21.6% and 12.9% faster than the GA-based and PSO-based methods, respectively on average.


Main Subjects

[1] N. S. Kim, J. Xiong, and W. W. Hwu, “Heterogeneous computing meets near-memory acceleration and high-level synthesis in the post-moore era,” IEEE Micro., vol. 37, no. 4, pp. 10-18, 2017.
[2] C. Pilato, S. Garg, K. Wu, R. Karri, and F. Regazzoni, “Securing hardware accelerators: A new challenge for high-level synthesis,” IEEE Embedded Systems Letters, vol. 10, no. 3, pp. 77-80, Sept. 2018.
[3] A. Sengupta, S. Bhadauria, and S. P. Mohanty, “TL-HLS: methodology for low cost hardware Trojan security aware scheduling with optimal loop unrolling factor during high level synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 4, pp. 655-668, April 2017.
[4] A. Mahapatra and B. C. Schafer, “VeriIntel2C: Abstracting RTL to C maximize high-Level synthesis design space exploration,” Integration, vol. 64, pp. 1-12, Jan. 2019.
[5] S. Das, R. Maity and N. P. Maity, “VLSI-based pipeline architecture for reversible image watermarking by difference expansion with high-level synthesis approach,” Circuits, Systems, and Signal processing, vol. 37, no. 4, pp. 1575-1593, April 2018.
[6] J. Zhao, L. Feng, S. Sinha, W. Zhang, Y. Liang, and B. He, “COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications," in Proc. IEEE/ACM International Conference on Computer-Aided Design, Irvine, CA, USA, 2017.

[7] P. Fezzardi, C. Pilato, and F. Ferrandi, “Enabling automated bug detection for IP-based design using high-level synthesis,” IEEE Design & Test, vol. 35, no. 5, pp. 54-62, April 2018.
[8] X. Tang, T. Jiang, A. Jones, and P. Banerjee, “Behavioral synthesis of data-dominated circuits for minimal energy implementation,” presented at the 18th International Conference on VLSI Design, Kolkata, India, 3-7 January 2005.
[9] N. Chabini and W. Wolf, “Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints,” IEEE Transactions on VLSI Systems, vol. 13, no. 10, pp. 1113–1126, 2005.
[10] A. Kumar and M. Bayoumi, “Multiple voltage-based scheduling methodology for low power in the high level synthesis,” in Proc. of the International Symposium on Circuits and Systems (ISCAS), pp. 371–379, 1999.
[11] A. K. Murugavel and N. Ranganathan, “A game theoretic approach for power optimization during behavioral synthesis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 6, pp. 1031–1043, 2003.
[12] R. K. Brayton, R. Camposano, G. De Micheli, R. Otten, and J. van Eijndhoven, “The Yorktown silicon compiler system,” in Silicon Compilation, D. D. Gajski, Ed. Reading, MA: Addison-Wesley, pp. 204–310, 1988.
[13] O. V. Nepomnyashchiy, I. V. Ryjenko, V. V. Shaydurov, N. Y. Sirotinina, and A. I. Postnikov, “The VLSI high-level synthesis for building onboard spacecraft control systems,” in Proc. The Scientific-Practical Conference “Research and Development 2016, pp. 229-238, 2018.
[14] S. P. Mohanty, R. Velagapudi, and E. Kougianos, “Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits,” in Proc. the Conference on Design, Automation and Test in Europe, pp. 1191–1196, 6-10 March 2006.
[15] S. Devadas and A. R. Newton, “Algorithms for hardware allocation in data path synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 8, no. 7, pp. 768-781, 1989.
[16] J. A. Nestor and G. Krishnamoorthy, “SALSA: A new approach to scheduling with timing constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 1107–1122, 1993.
[17] S. Rajmohan and N. Ramasubramanian, “Group influence based improved firefly algorithm for design space exploration of datapath resource allocation,” Applied Intelligence, vol. 49, no. 6, pp. 2084-2100, June 2019.
[18] G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York 1994.
[19] R. Camposano, “Path-based scheduling for synthesis,” IEEE Trans. Comput. -Aided Des., vol. 10, pp. 85–93, 1991.
[20] S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, 2004.
[21] S. Rajmohan and N. Ramasubramanian, “A Memetic algorithm based design space exploration for datapath resource allocation during high level synthesis,” Journal of Circuits, Systems and Computers, DOI:10.1142/s0218126620500012, 2019.
[22] S. Bhadauria and A. Sengupta, “Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis,” Applied Mathematics and Computation, vol. 269, pp. 265-278, Oct. 2015.
[23] V. Krishnan and S. Katkoori, “A genetic algorithm for the design space exploration of datapaths during high-level synthesis,” IEEE Trans. Evol. Comput., vol. 10, no. 3, pp. 213–229, 2006.
[24] A. Sengupta and R. Sedaghat, “Integrated scheduling, allocation and binding in high level synthesis using multi structure Genetic Algorithm based design space exploration,” in Proc.
The 12th International Symposium on Quality Electronic Design, pp. 1-9, 14-16 March 2011.
[25] D. S. Harish Ram, M. C. Bhuvaneswari, and S. S. Prabhu, “A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths,” VLSI Design, vol. 2012, pp. 1-12, 2012.
[26] R. F. Abdel-kader, “Particle swarm optimization for constrained instruction scheduling,” VLSI Design, vol. 2008, no. 4, pp. 1-7, January 2008.
[27] S. A. Hashemi and B. Nowrouzian, “A novel particle swarm optimization for high-level synthesis of digital filters,” in Proc. The 25th IEEE International Symposium on Circuits and Systems, pp 580–583, 20-23 May 2012.
[28] C. Pilato, D. Loiacono, A. Tumeo, F. Ferrandi, P. L. Lanzi, and D. Sciuto, “Speeding-up expensive evaluations in high-level synthesis using solution modeling and fitness inheritance,” Computational Intelligence in Expensive Optimization Problems, vol. 2, pp. 701–723, 2010.
[29] G. Wang, W. Gong, B. DeRenzi, and R. Kastner, “Design space exploration using time and resource duality with the ant colony optimization,” in Proc. The 43rd ACM/IEEE Design Automation Conference, pp. 451–454, 24-28 July 2006.
[30] C. Gopalakrishnan and S. Katkoori, “Tabu search based behavioral synthesis of low leakage datapaths,” in Proc. IEEE Computer Society Annual Symposium on VLSI, pp. 260–261, 19-20 Feb. 2004.
[31] R. Kianzad and H. M. Kordy, “Automatic sleep stages detection based on EEG signals using combination of classifiers,” Journal of Electrical and Computer Engineering Innovations (JECEI), vol. 1, no. 2, pp. 99-105, Spring 2014.
[32] A. Khalili, A. Rastegarnia, V. Vahidpour, and Md. K. Islam, “Adaptive-filtering-based algorithm for impulsive noise cancellation from ECG signal,” Journal of Electrical and Computer Engineering Innovations (JECEI), vol. 4, no. 2, pp. 169-176, Autumn 2016.
[33] A. Ghanbari, A. Sadr, and M. Nikoo, “High speed delay-locked loop for multiple clock phase generation,” Journal of Electrical and Computer Engineering Innovations (JECEI), vol. 1, no. 1, pp. 19-27, Autumn 2013.
[34] M. Moradi and M. R. Sadeghi, "Combining and steganography of 3-d face textures,” Journal of Electrical and Computer Engineering Innovations (JECEI), vol. 5, no. 2, pp. 93-100, Autumn 2017.
[35] S. P. Mohanty, N. Ranganathan, E. Kougianos, and P. Patra, Low-Power High-Level Synthesis for Nanoscale CMOS Circuits, Springer US, India 2008.
[36] S. Mirjalili, “Moth-flame optimization algorithm: A novel nature-inspired heuristic paradigm,” Knowledge-Based Systems, vol. 89, pp. 228-249, Nov. 2015.
[37] Z. Li, Y. Zhou, S. Zhang, and J. Song “Levy-flight moth-flame algorithm for function optimization and engineering design problems,” Mathematical Problems in Engineering, vol. 2016.
[38] N. Muangkote, K. Sunat, and S. Chiewchanwattana, “Multilevel thresholding for satellite image segmentation with moth-flame based optimization,” presented at the 13th International Joint Conference on Computer Science and Software Engineering (JCSSE), Khon Kaen, Thailand, July 2016.
[39] K. Kaur, U. Singh, and R. Salgotra, “An enhanced moth flame optimization,” Neural Comput. & Applic., 2018, Available:
[40] M. C. Bhuvaneswari, Application of Evolutionary Algorithms for Multi-Objective Optimization in VLSI and Embedded Systems, Springer, India 2015.