Electronics
S. Rahmati; E. Farshidi; J. Ganji
Abstract
Background and Objectives: In recent decades, due to the effect of the short channel, the use of CMOS transistors in the nanoscale has become a major concern. One option to deal with this issue is the use of nano-transistors. Methods: Using nano-transistors and multi-valued logic (MVL) can reduce the ...
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Background and Objectives: In recent decades, due to the effect of the short channel, the use of CMOS transistors in the nanoscale has become a major concern. One option to deal with this issue is the use of nano-transistors. Methods: Using nano-transistors and multi-valued logic (MVL) can reduce the level of chips and connections and have a direct impact on power consumption. The present study reports the design of a new method of Multiplexers (MUXs) based on quaternary logic and transistors of carbon nanotubes (CNTFET) and having a new look at the layout and use of MUXs. Results:The use of special rotary functions and unary operators in Quaternary logic in the design of MUXs reduced the number of CNTFETs from 27% to 54%. Also, the use of MUXs in the Adder structure resulted in a 54% reduction in Power Delay Product (PDP) and a 17.5% to 85.6% reduction in CNTFET counts. Conclusion: The simulated results display a significant improvement in the fabrication of Adders, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits were evaluated under various operating conditions. The results show the stability of the proposed circuits.======================================================================================================Copyrights©2020 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
Z. Kordrostami; S. Hamedi; F. Khalifeh
Abstract
Background and Objectives: High electron mobility transistors (HEMTs) are designed so that they are able to work at higher frequencies than conventional transistors and this has made them an attractive topic of research. Methods: Two developed designs of InGaAs/InAlAs high electron mobility transistors ...
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Background and Objectives: High electron mobility transistors (HEMTs) are designed so that they are able to work at higher frequencies than conventional transistors and this has made them an attractive topic of research. Methods: Two developed designs of InGaAs/InAlAs high electron mobility transistors have been studied. The proposed laterally contacted HEMTs satisfy the desired high frequency characteristics and are good candidates for high frequency applications. Two kinds of HEMTs have been designed and simulated: single-gate laterally contacted HEMT (SGLC-HEMT) and doublegate laterally contacted HEMT (DGLC-HEMT). Results: The proposed SGLC-HEMT exhibits 111 GHz current-gain cut-off frequency. By using double-gate design, the current-gain cut-off frequency has been increased to 256 GHz. The simulation results show that the maximum oscillation frequency for the proposed SGLC and DGLC HEMTs, are 410 GHz and 768 GHz, respectively. The maximum value of transconductance (gm) for SGLC-HEMT is obtained 620 mS/mm while it is 1130 mS/mm for DGLC-HEMT. Conclusion: In order to increase the fT and fmax, instead of decreasing the gate length which is a restricted solution because of short channel effects, a very efficient structure was proposed. The designed HEMT benefits from laterally source and drain contacts. The results showed superior performance of the laterally contacted HEMTs compared to top contacted ones. The best frequency response was obtained for DGLC-HEMT. The proposed DG-HEMT design could improve the current-gain cut-off frequency and maximum oscillation frequency to 256 GHz and 768 GHz, respectively. The comparison of the performance of the DGLC-HEMT with SGLC-HEMT and with previously reported double gate HEMTs, verified the significant improvements in DC and AC characteristics of the HEMTs caused by the proposed design.======================================================================================================Copyrights©2019 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
A. Mouri Zadeh Khaki; E. Farshidi; K. Ansari Asl
Abstract
Background and Objectives: Beside acceptable performance, power consumption and chip area are important issues in embedded systems that should be taken into consideration. Methods: In this paper, a novel continuous-time 1-1 MASH ∆∑ Time-to-digital converter (TDC) is presented. Since the proposed ...
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Background and Objectives: Beside acceptable performance, power consumption and chip area are important issues in embedded systems that should be taken into consideration. Methods: In this paper, a novel continuous-time 1-1 MASH ∆∑ Time-to-digital converter (TDC) is presented. Since the proposed design utilizes 12-bit quantizer based on Gated Switched-Ring Oscillator (GSRO) for both stages, it has been implemented all-digitally. By using a novel structure, only one multi-bit counter is employed for both stages, therefore the required hardware for implementation of this work is much less than conventional TDCs. As a result, complexity, chip area and power consumption would decrease considerably. Results: We implemented the proposed design prototype on an Altera Stratix IV FPGA board. Measured results demonstrate that although this work uses less complex architecture in comparison with previous works, it provides appropriate performance such as 60.7 dB SNR within 8 MHz signal bandwidth at 400 MHz sampling rate while consuming 2.79 mW. Conclusion: Experimental results reveals suitability of the proposed TDC to be incorporated in fast and accurate applications such as ADPLLs and high-resolution photoacoustic tomography. Also, by adjusting the proposed novel structure with more stages higher order of noise-shaping can be attained to enhance SNR and time-resolution further.======================================================================================================Copyrights©2019 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
F. Abdi; P. Amiri; M.H. Refan
Abstract
Background and Objectives: Adaptive algorithm adjusts the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor. Methods: Vedic mathematics ...
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Background and Objectives: Adaptive algorithm adjusts the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor. Methods: Vedic mathematics is used to implement the multiplier and the divider operations in the VFF equations. The linear exponentially weighted recursive least squares as the main algorithm is implemented in many applications such as the adaptive controller, the system identification, active noise cancellation techniques, and etc. The DCD method calculates the inverse matrix in the ERLS algorithm and decreases the resources used in the field-programmable gate array, also the designer can use the cheaper FPGA board to implement the adaptive algorithm because the method doesn't need lots of resources. Results: The proposed method is implemented with ISE software on the Spartan 6 Xilinx board. The proposed algorithm calculates the multiplication result with less than 15ns time and reduces the used FPGA resources to lower than 20% as compared with the classic RLS. Conclusion: The proposed method decreases the area and increases the computation speed. Also, it leads to implementing complex algorithms with simple structures and high technology.======================================================================================================Copyrights©2019 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
M. Karbalaei; D. Dideban; N. Moezi
Abstract
Background and Objectives: In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated. Methods: The dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor is a Silicon-channel TFET ...
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Background and Objectives: In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated. Methods: The dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor is a Silicon-channel TFET with two isolated metal gates (main gate and auxiliary gate) and a source pocket in the channel close to the source-channel junction to increase the carrier tunneling rate. Results: For further enhancement in the tunneling rate, source doping near the source-channel junction, i.e., underneath the auxiliary gate is heavily doped to create more band bending in energy band diagram. Retrograde doping in the channel along with auxiliary gate over the source region also improve device subthreshold swing and leakage current. Based on our simulation results, excellent electrical characteristics with ION/IOFF ratio > 109, point subthreshold swing (SS) of 6 mV/dec and high gm/ID ratio at room temperature shows that this tunneling FET can be a promising device for low power applications Conclusion: In order to increase the ON-current in this device, we utilized several methods including incorporation of high-K material in top oxide, source pocket in channel and a thin auxiliary gate with high workfunction over the source region. Incorporating auxiliary gate over the source also caused a barrier formation in the energy band diagram profile of this device which it leds electron concentration in the channel, subthreshold swing and OFF-current to be reduced.======================================================================================================Copyrights©2019 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
P. Halvaee; M.S. Beigi
Abstract
Background and Objectives: In this work, porous nanoparticles of ferrite cobalt were prepared by dissolving CoCl2.6H2O and FeCl3 in ethylene glycol in a hydrothermal process. Using ethylene glycol instead of DI water as a solvent would cause to provide porous structure of ferrite cobalt. Methods: In ...
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Background and Objectives: In this work, porous nanoparticles of ferrite cobalt were prepared by dissolving CoCl2.6H2O and FeCl3 in ethylene glycol in a hydrothermal process. Using ethylene glycol instead of DI water as a solvent would cause to provide porous structure of ferrite cobalt. Methods: In the present paper, 0.05 ml of colloidal fluid of fabricated nanostructure was injected on interdigitated electrodes (IDE) on a printed circuit board (PCB) substrate by a drop casting process. Morphological and structural characterizations of structure were investigated by X-ray diffraction and scanning electron microscopy and the obtained results of analyses show the porous nanostructure of the material. Results: Sensor's performance in detection of gas vapors was evaluated in different temperatures which has the best response (20.38% for 100ppm methanol vapors) for methanol vapors at room temperature. performance of sensor in selection of methanol vapors, chemical stability and repeatability of that, makes it useful to profit it in different fields and industries. Conclusion: Porous nanoparticles of CoFe2O4 were prepared by a hydrothermal process. By benefiting of XRD analysis and SEM images, porosity of nanostructure was approved. Response of sensor in different temperatures was measured. At room temperature, it has the best response of 21.38% for 100 ppm methanol vapors. Room temperature working of sensor causes reducing in power consumption and decreasing risks of working in high temperatures. This sensor has a good selectivity to methanol vapors in presence of ethanol, acetone, methane and LPG vapors. Repeatability and chemical stability of sensor in long times of working were approved.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
J. Khosravi; M. Shams Esfandabadi; R. Ebrahimpour
Abstract
Background and Objectives: There are numerous applications for image registration (IR). The main purpose of the IR is to find a map between two different situation images. In this way, the main objective is to find this map to reconstruct the target image as optimum as possible. Methods: Needless to ...
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Background and Objectives: There are numerous applications for image registration (IR). The main purpose of the IR is to find a map between two different situation images. In this way, the main objective is to find this map to reconstruct the target image as optimum as possible. Methods: Needless to say, the IR task is an optimization problem. As the optimization method, although the evolutionary ones are sometimes more effective in escaping the local minima, their speed is not emulated the mathematical ones at all. In this paper, we employed a mathematical framework based on the Newton method. This framework is suitable for any efficient cost function. Yet we used the sum of square difference (SSD). We also provided an effective strategy in order to avoid sticking in the local minima. Results: The proposed newton method with SSD as a cost function expresses more decent speed and accuracy in comparison to Gradient descent and genetic algorithms methods based on presented criteria. By considering SSD as the model cost function, the proposed method is able to introduce, respectively, accurate and fast registration method which could be exploited by the relevant applications. Simulation results indicate the effectiveness of the proposed model. Conclusion: The proposed innovative method based on the Newton optimization technique on separate cost functions is able to outperform regular Gradient descent and genetic algorithms. The presented framework is not based on any specific cost function, so any innovative cost functions could be effectively employed by our approach. Whether the objective is to reach accurate or fast results, the proposed method could be investigated accordingly.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
H. Firoozi; M. Imanieh
Volume 6, Issue 1 , Winter and Spring 2018, , Pages 7-13
Abstract
< p>Background and Objectives: In this article, the functionality of solar cells structure based on CuIn1-xGaxSe2 is investigated. This type of solar cell consists of different layers, namely, ZnO (TCO layer), Cd_S (Buffer layer), CIGS (Absorbent layer), and MO (Substrate layer). Two layers, Cd_S ...
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< p>Background and Objectives: In this article, the functionality of solar cells structure based on CuIn1-xGaxSe2 is investigated. This type of solar cell consists of different layers, namely, ZnO (TCO layer), Cd_S (Buffer layer), CIGS (Absorbent layer), and MO (Substrate layer). Two layers, Cd_S and CIGS, form a PN Junction. < p>Methods: CIGS thin film solar cell is simulated using SILVACO software. The absorbent layer doping was originally changed. Later doping was kept constant and P-type layer of InAsP was added. Their effect on cell function was observed and examined. It was observed that after doping some parameters of the solar cell have improved whilst some others have decreased. It was also concluded that examined increase or decrease in the amount of dopant would reduce our efficiencies of solar cell. < p>Results: Added the InAsP layer leads to increased open circuit voltage, short circuit current and the solar cell power, consequently gives the efficiency about 33.2%, which is an acceptable efficiency. < p>Conclusion: It was clear that extreme increase or decrease in the amount of dopant in the absorbent layer can change solar cell parameters, and can improve cell functionality. < p>The amount of dopants can also alter some other solar cell parameters which are not desirable, the added InAsP layer leads to increased open circuit voltage, and short circuit current and the solar cell power, consequently gives the about 33.2%, efficiency which is an acceptable efficiencies.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
M. Feli; F. Parandin
Abstract
Background and Objectives: Solar cell is an electronic device which harvest photovoltaic effect and transform light energy to electricity. An efficient double junction InGaN/CIGS solar cell can be simulated using Silvaco ATLAS software. In this study, a thin CdS top cover layer is used as the anti-reflector ...
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Background and Objectives: Solar cell is an electronic device which harvest photovoltaic effect and transform light energy to electricity. An efficient double junction InGaN/CIGS solar cell can be simulated using Silvaco ATLAS software. In this study, a thin CdS top cover layer is used as the anti-reflector layer. Methods: To reach the current matching condition, changing the thickness of this CdS layer, we can enhance the short-circuit currents of both the top and bottom cells. To gain a desired efficiency, different design parameters, such as the doping concentrations and the thicknesses of the various layers of the cell are optimized. This cell is designed to be used in a real environmental situation. Results: By using the appropriate parameters, and under matching conditions, the efficiency is optimized as well as the filling factor is increased. Considering the proposed structure and the simulation results, an optimum efficiency of 41.87% is achieved and also the obtained fill factor is equal to 75.16%. Conclusion: In this paper, a new structure for an efficient double junction InGaN/CIGS solar cell, was proposed. In our proposed structure, a thin CdS layer is used as the anti-reflector layer. To get a desired efficiency, different design parameters, such as the doping concentrations and the thicknesses of various layers of the cells were optimized. ======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
S. Ranjbaran; A. Roudbari; S. Ebadollahi
Abstract
Background and Objectives: Using field calibration methods without precision laboratory equipment, systematic faults of inertial sensors can be reduced and measurement accuracy can be increased. Methods: In this paper, a simple and fast method called improved least squares is used to find calibration ...
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Background and Objectives: Using field calibration methods without precision laboratory equipment, systematic faults of inertial sensors can be reduced and measurement accuracy can be increased. Methods: In this paper, a simple and fast method called improved least squares is used to find calibration coefficients of an accelerometer including bias, scale factor and non-orthogonality. In this method, this principal is used that the magnitude of acceleration measured by accelerometer in static condition is equal to the magnitude of gravity vector and a cost function is then defined. Also, in gyroscope field calibration, sensor is rotated manually around all three axes separately and then it is put in the static mode. Changes in the angle obtained from gyroscope at each movement are compared with the ones obtained from the calibrated accelerometer. Calibration coefficients including bias and scale factor are obtained using least squares method. Results: Simulation results in MATLAB show that the measurement accuracy of accelerometer after calibration has improved by about 60% and the accuracy of the gyroscope has increased by about 40%. Also, comparison with the other methods proves that the proposed method performs well in the accuracy, speed, time required, and the effect of noise changes. Conclusion: This paper by finding a fast, simple, and low-cost field calibration method to calibrate MEMS accelerometer and gyroscope without using accurate laboratory equipment can help a wide range of industries that use advanced and expensive sensors or use expensive laboratory equipment to calibrate their sensors, to decrease their costs.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
