Low Computational Complexity and High Computational Speed in Leading DCD ERLS Algorithm

Abdi, F.; Amiri, P.; Refan, M.H.

doi:10.22061/jecei.2019.5666.243

Document Type : Original Research Paper

Authors

Department of Electrical Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran

https://doi.org/10.22061/jecei.2019.5666.243

Abstract

Background and Objectives: Adaptive algorithm adjusts the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor.
Methods: Vedic mathematics is used to implement the multiplier and the divider operations in the VFF equations. The linear exponentially weighted recursive least squares as the main algorithm is implemented in many applications such as the adaptive controller, the system identification, active noise cancellation techniques, and etc. The DCD method calculates the inverse matrix in the ERLS algorithm and decreases the resources used in the field-programmable gate array, also the designer can use the cheaper FPGA board to implement the adaptive algorithm because the method doesn't need lots of resources.
Results: The proposed method is implemented with ISE software on the Spartan 6 Xilinx board. The proposed algorithm calculates the multiplication result with less than 15ns time and reduces the used FPGA resources to lower than 20% as compared with the classic RLS.
Conclusion: The proposed method decreases the area and increases the computation speed. Also, it leads to implementing complex algorithms with simple structures and high technology.

Keywords

20.1001.1.23223952.2019.7.1.3.5

Main Subjects

Electronics

Open Access

This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit: http://creativecommons.org/licenses/by/4.0/

Publisher’s Note

JECEI Publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Publisher

Shahid Rajaee Teacher Training University

References

[1] S. Haykin, Adaptive Filter Theory, 4nd ed. Upper Saddle River, NJ: Prentice-Hall, 2002.

[2] M. Ned, T. M. Undeland, W. P. Robbins, Power Electronics: Converters, Applications, and Design, 3rd ed., John Wiley & Sons, Inc., 2003.

[3] F. Abdi, P. Amiri, "Design and implementation of adaptive FxLMS on FPGA for online active noise cancellation," Journal of the Chinese Institute of Engineers, 41(2): 132-140, 2018.

[4] M. Algreer, M. Armstrong, D. Giaouris, "Active on-line system identification of switch mode dc-dc power converter based on efficient recursive DCD-IIR adaptive filter," IEEE Transactions on Power Electronics, 27: 4425-4435, 2012.

[5] P. G. Vasundhara, N. Puhan, "An improved block adaptive system for effective feedback cancellation in hearing aids," Digital Signal Processing, 48: 216–225, 2015.

[6] R. Rybaniec et al., "FPGA based RF and piezo controllers for SRF cavities in CW mode," in Proc. 2016 IEEE-NPSS Real Time Conference (RT): 1-2, 2016.

[7] M. Shirazi, R. Zane, D. Maksimovic, "An auto-tuning digital controller for DC-DC power converters based on online frequency-response measurement," IEEE Trans. Power Electron., 24(11): 2578–2588, 2009.

[8] P. B. Bhat, V. K. Prasanna, C. S. Raghavendra, "Adaptive communication algorithms for distributed heterogeneous systems," in Proc. The Seventh International Symposium on High Performance Distributed Computing: 310-321, 1998.

[9] Y. Guo, H. Xiao, Qiang Fu, "Least square support vector data description for HRRP-based radar target recognition," Applied Intelligence, 46: 365-372, 2016.

[10] P. K. Sethy, S. Bhattacharya, "Interference cancellation in adaptive filtering through LMS algorithm using TMS320C6713DSK," International Journal of Electronics and Communication Engineering, 5(2): 113-124, 2012.

[11] R. Qureshi, S. A. R. Rizvi, S. H. Musavi, S. Khan, K. Khurshid, "Performance analysis of adaptive algorithms for removal of low frequency noise from ECG signal," presented at the 2017 International Conference on Innovations in Electrical Engineering and Computational Technologies (ICIEECT), Karachi, Pakistan, 2017.

[12] M. M. Peretz, S. Ben-Yaakov, "Time-domain identification of PWM converters for digital controllers design," in Proc. IEEE Power Electronics Specialists Conference): 809–813, 2007.

[13] Y. V. Zakharov, B. Weaver, T. C. Tozer, "Novel signal processing technique for real-time solution of the least squares problem," in Proc. 2nd International Workshop on Signal Processing for Wireless Communications: 155-159, 2004.

[14] G. H. Golub, C. F. Van Loan, Matrix Computations, The Johns Hopkins University Press, Baltimore, 3rd edition, 1996.

[15] S. D. Muruganathan, A. B. Sesay, "A QRD-RLS-based predistortion scheme for high-power amplifier linearization," IEEE Trans. Circuits and Systems - II: Express Briefs, 53(10): 1108–1112, 2006.

[16] Y. V. Zakharov, T. C. Tozer, "Multiplication-free iterative algorithm for LS problem," Electronics Letters, 40(9): 567–569, April, 2004.

[17] Z. Liu, J. V. McCanny, G. Lightbody, R. L. Walke, "Generic SoC QR array processor for adaptive beam forming," IEEE Transactions on Circuits and Systems II: Express Briefs, 50, no 4): 169–175, April 2003.

[18] D. S. Watkins, Fundamentals of matrix computations, Hoboken, N. J., Wiley, 2002.

[19] L. Jie, "DCD algorithm: architectures, FPGA implementations and applications," Ph.D. dissertation, University of York Nov 2008.

[20] Y. Zakharov, G. White, L. Jie, "Fast RLS algorithm using dichotomous coordinate descent iterations," presented at the 2007 Conference Record of the Forty-First Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, 2007.

[21] G. K. Boray, M. D. Srinath, "Conjugate gradient techniques for adaptive filtering," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 39(1): 1–10, 1992.

[22] J. Morroni, R. Zane, D. Maksimovic, "An online stability margin monitor for digitally controlled switched-mode power supplies,” IEEE Transactions on Power Electronics, 24(11): 2639-2648, 2009.

[23] L. Jie, Y. V. Zakharov, B. Weaver, “Architecture and FPGA design of dichotomous coordinate descent algorithms," IEEE Transactions on Circuits and Systems I: Regular Papers, 56(11): 2425-2438, 2009.

[24] P. S. Chang, A. N. Willson Jr., "Analysis of conjugate gradient algorithms for adaptive filtering," IEEE Transactions on Signal Processing, 48(2): 409–418, 2000.

[25] A. S. K. Vamsi, S. R. Ramesh, "An efficient design of 16 bit mac unit using vedic mathematics," presented at the 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, 2019.

[26] L. Zhang, Y. Cai, ChunguangLi-an, R. C. Lamare, "Variable forgetting factor mechanisms for diffusion recursive least squares algorithm in sensor networks," EURASIP Journal on Advances in Signal Processing, 2017(1): 1-23, 2017.

[27] C. R. S. Hanuman, J. Kamala, "Hardware implementation of 24-bit vedic multiplier in 32-bit floating-point divider," presented at the 2018 4th International Conference on Electrical, Electronics and System Engineering (ICEESE), Kuala Lumpur, Malaysia, 2018.

[28] A. Menon, R. J. Renjith, "Implementation of 24 Bit high speed floating point Vedic multiplier," International Journal of Advance Engineering and Research Development, 4(5): 742-749, 2017.

[29] M. lloyde George, "Novel mantissa similarity investigator for path delay reduction of product mantissa calculation," presented at the 25th International Conference, New York, USA, July 2018.

[30] M. Maraş, E. N. Ayvaz, A. Özen, "A novel adaptive variable forgetting factor RLS algorithm," presented at the 26th Signal Processing and Communications Applications Conference (SIU), Izmir, Turkey, 2018.

[31] S. C. Chan, H. J. Tan, J.Q Lin, "A new local polynomial modeling based variable forgetting factor and variable regularized PAST algorithm for subspace tracking," IEEE Transactions on Aerospace and Electronic Systems, 54 (3): 1530-1544, 2018.

[32] Y. Lu, Q. Li, Z. Pan, Y. Liang, "Prognosis of bearing degradation using gradient variable forgetting factor RLS combined with time series model," IEEE Access, 6: 10986 – 10995, 2018.

[33] S. Asif Hossain, A. Mallik, Md. Arman Arefin, "A signal processing approach to estimate underwater network cardinalities with lower complexity," JECEI, 5(2): 131-138, 2017.

[34] J. Khosravi, M. Shams Esfandabadi, R. Ebrahimpour, "Image registration based on sum of square difference cost function," JECEI, 6(2): 263-271, 2018.

LETTERS TO EDITOR

Journal of Electrical and Computer Engineering Innovations (JECEI) welcomes letters to the editor for the post-publication discussions and corrections which allows debate post publication on its site, through the Letters to Editor. Letters pertaining to manuscript published in JECEI should be sent to the editorial office of JECEI within three months of either online publication or before printed publication, except for critiques of original research. Following points are to be considering before sending the letters (comments) to the editor.

[1] Letters that include statements of statistics, facts, research, or theories should include appropriate references, although more than three are discouraged.

[2] Letters that are personal attacks on an author rather than thoughtful criticism of the author’s ideas will not be considered for publication.

[3] Letters can be no more than 300 words in length.

[4] Letter writers should include a statement at the beginning of the letter stating that it is being submitted either for publication or not.

[5] Anonymous letters will not be considered.

[6] Letter writers must include their city and state of residence or work.

[7] Letters will be edited for clarity and length.

Name *

Email Address *

Affiliation *

Comments *

Security Code *

Journal of Electrical and Computer Engineering Innovations (JECEI)

Low Computational Complexity and High Computational Speed in Leading DCD ERLS Algorithm

References

References

Send comment about this article

Volume 7, Issue 1
January 2019
Pages 19-26

Low Computational Complexity and High Computational Speed in Leading DCD ERLS Algorithm

References

References

Send comment about this article

Volume 7, Issue 1January 2019Pages 19-26

Volume 7, Issue 1
January 2019
Pages 19-26