Document Type : Original Research Paper


1 Dept. of Electrical Engineering, Faculty of Electrical and Computer Engineering, University of Birjand, Birjand, Iran

2 Department of Electrical Engineering, Faculty of Engineering, University of Birjand, Birjand, Iran


Background and Objectives: High-level synthesis (HLS) is one of the substantial steps in designing VLSI digital circuits. The primary purpose of HLS is to minimize the digital units used in the system to improve their power, delay, and area.
Methods: In the modified MFO algorithm presented in this paper, a hyperbolic spiral is chosen as the update mechanism of moths. Also, by presenting a new approach, a paramount issue involved in applying meta-heuristic methods for solving HLS problems of VLSI circuits has been disentangled.
Results: By comparing the performance of the proposed method with Genetic algorithm (GA)-based method and particle swarm optimization (PSO)-based method for the synthesis of the digital filters, it is concluded that the proposed method has the higher ability in the HLS of data path in digital filters. The best improvement is 2.78% for the delay (latency), 6.51% for the occupied area of the chip and 6.93% in power consumption. Another feature of the proposed method is its high-speed in finding optimal solutions, in a manner which, more than 21.6% and 12.9% faster than the GA-based and PSO-based methods, respectively on average.
Conclusion: The most important very large scale integration (VLSI) circuits are digital filters and transformers, which are widely used in audio and video processing, medical signal processing, and telecommunication systems. The complex, expansive, and discrete nature of design space in high-level synthesis problems has made them one of the most difficult problems in VLSI circuit design.

©2019 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.


Main Subjects

[1] N. S. Kim, J. Xiong, W. W. Hwu, "Heterogeneous computing meets near-memory acceleration and high-level synthesis in the post-moore era," IEEE Micro., 37(4): 10-18, 2017.

[2] C. Pilato, S. Garg, K. Wu, R. Karri, F. Regazzoni, "Securing hardware accelerators: A new challenge for high-level synthesis," IEEE Embedded Systems Letters, 10(3): 77-80, 2018.

[3] A. Sengupta, S. Bhadauria, S. P. Mohanty, "TL-HLS: methodology for low cost hardware Trojan security aware scheduling with optimal loop unrolling factor during high level synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 36(4): 655-668, 2017.

[4] A. Mahapatra, B. C. Schafer, "VeriIntel2C: Abstracting RTL to C maximize high-Level synthesis design space exploration," Integration, 64): 1-12, 2019.

[5] S. Das, R. Maity , N. P. Maity, "VLSI-based pipeline architecture for reversible image watermarking by difference expansion with high-level synthesis approach," Circuits, Systems, and Signal processing, 37(4): 1575-1593, 2018.

[6] J. Zhao, L. Feng, S. Sinha, W. Zhang, Y. Liang, B. He, "COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications," in Proc. 2017 IEEE/ACM International Conference on Computer-Aided Design, Irvine, CA, USA.

[7] P. Fezzardi, C. Pilato, F. Ferrandi, "Enabling automated bug detection for IP-based design using high-level synthesis," IEEE Design & Test, 35(5): 54-62, 2018.

[8] X. Tang, T. Jiang, A. Jones, P. Banerjee, "Behavioral synthesis of data-dominated circuits for minimal energy implementation," presented at the 18th International Conference on VLSI Design, Kolkata, India, 3-7 2005.

[9] N. Chabini, W. Wolf, "Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints," IEEE Transactions on VLSI Systems, 13(10): 1113–1126, 2005.

[10]  A. Kumar, M. Bayoumi, "Multiple voltage-based scheduling methodology for low power in the high level synthesis," in Proc. 1999 the International Symposium on Circuits and Systems (ISCAS): 371–379.

[11] A. K. Murugavel, N. Ranganathan, "A game theoretic approach for power optimization during behavioral synthesis," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(6): 1031–1043, 2003.

[12] R. K. Brayton, R. Camposano, G. De Micheli, R. Otten, J. van Eijndhoven, "The Yorktown silicon compiler system," in Silicon Compilation, D. D. Gajski, Ed. Reading, MA: Addison-Wesley): 204–310, 1988.

[13] O. V. Nepomnyashchiy, I. V. Ryjenko, V. V. Shaydurov, N. Y.  Sirotinina, A. I. Postnikov, "The VLSI high-level synthesis for building onboard spacecraft control systems," in Proc. 2018 the Scientific-Practical Conference “Research and Development: 229-238, 2016.

[14] S. P. Mohanty, R. Velagapudi, E. Kougianos, "Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits," in Proc. 2006 the Conference on Design, Automation and Test in Europe: 1191–1196.

[15] S. Devadas, A. R. Newton, "Algorithms for hardware allocation in data path synthesis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(7): 768-781, 1989.

[16] J. A. Nestor, G. Krishnamoorthy, "SALSA: A new approach to scheduling with timing constraints," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12): 1107–1122, 1993.

[17] S. Rajmohan, N. Ramasubramanian, "Group influence based improved firefly algorithm for design space exploration of datapath resource allocation," Applied Intelligence, 49(6): 2084-2100, 2019.

[18] G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York 1994.

[19] R. Camposano, "Path-based scheduling for synthesis," IEEE Trans. Comput. -Aided Des., 10: 85–93, 1991.

[20] S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, 2004.

[21] S. Rajmohan, N. Ramasubramanian, "A Memetic algorithm based design space exploration for datapath resource allocation during high level synthesis," Journal of Circuits, Systems and Computers.

[22] S. Bhadauria, A. Sengupta, "Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis," Applied Mathematics and Computation, 269): 265-278, 2015.

[23] V. Krishnan, S. Katkoori, "A genetic algorithm for the design space exploration of datapaths during high-level synthesis," IEEE Trans. EComput., 10(3): 213–229, 2006.

[24] A. Sengupta, R. Sedaghat, "Integrated scheduling, allocation and binding in high level synthesis using multi structure Genetic Algorithm based design space exploration," in Proc. 2011 The 12th International Symposium on Quality Electronic Design: 1-9.

[25] D. S. Harish Ram, M. C. Bhuvaneswari, S. S. Prabhu, "A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths," VLSI Design, 2012: 1-12, 2012.

[26] R. F. Abdel-kader, "Particle swarm optimization for constrained instruction scheduling," VLSI Design, 2008(4): 1-7, January 2008.

[27] S. A. Hashemi, B. Nowrouzian, "A novel particle swarm optimization for high-level synthesis of digital filters," in Proc. 2012 The 25th IEEE International Symposium on Circuits and Systems, pp 580–583, 2012.

[28] C. Pilato, D. Loiacono, A. Tumeo, F. Ferrandi, P. L. Lanzi, D. Sciuto, "Speeding-up expensive evaluations in high-level synthesis using solution modeling and fitness inheritance," Computational Intelligence in Expensive Optimization Problems, 2: 701–723, 2010.

[29] G. Wang, W. Gong, B. DeRenzi, R. Kastner, "Design space exploration using time and resource duality with the ant colony optimization," in Proc. 2006 The 43rd ACM/IEEE Design Automation Conference): 451–454, 2016.

[30] C. Gopalakrishnan, S. Katkoori, "Tabu search based behavioral synthesis of low leakage datapaths," in Proc. 2004 IEEE Computer Society Annual Symposium on VLS): 260–261, 2004.

[31] R. Kianzad, H. M. Kordy, "Automatic sleep stages detection based on EEG signals using combination of classifiers," Journal of Electrical and Computer Engineering Innovations (JECEI), 1(2): 99-105, 2014.

[32] A. Khalili, A. Rastegarnia, V. Vahidpour, Md. K. Islam, "Adaptive-filtering-based algorithm for impulsive noise cancellation from ECG signal," Journal of Electrical and Computer Engineering Innovations (JECEI), 4(2): 169-176, 2016.

[33] A. Ghanbari, A. Sadr, M. Nikoo, "High speed delay-locked loop for multiple clock phase generation," Journal of Electrical and Computer Engineering Innovations (JECEI), 1(1): 19-27, 2013.

[34] M. Moradi, M. R. Sadeghi, "Combining and steganography of 3-d face textures," Journal of Electrical and Computer Engineering Innovations (JECEI), 5(2): 93-100, 2017.

[35] S. P. Mohanty, N. Ranganathan, E. Kougianos, P. Patra, Low-Power High-Level Synthesis for Nanoscale CMOS Circuits, Springer US, India 2008.

[36] S. Mirjalili, "Moth-flame optimization algorithm: A novel nature-inspired heuristic paradigm," Knowledge-Based Systems, 89: 228-249, 2015.

[37] Z. Li, Y. Zhou, S. Zhang, J. Song, "Levy-flight moth-flame algorithm for function optimization and engineering design problems," Mathematical Problems in Engineering, 2016.

[38] N. Muangkote, K. Sunat, S. Chiewchanwattana, "Multilevel thresholding for satellite image segmentation with moth-flame based optimization," presented at the 13th International Joint Conference on Computer Science and Software Engineering (JCSSE), Khon Kaen, Thailand, 2016.

[39] K. Kaur, U. Singh, R. Salgotra, "An enhanced moth flame optimization," Neural Comput. & Applic., 2018.

[40] M. C. Bhuvaneswari, Application of Evolutionary Algorithms for Multi-Objective Optimization in VLSI and Embedded Systems, Springer, India 2015.

[41] M. Jhamb, Garima, H. Loohani, "Design, implementation and performance comparison of multiplier topologies in power-delay space," Engineering Science and Technology, an International Journal, 19(1): 355-363, 2016.

[42] S. S. Choong, L. P. Wong, C. P. Lim, "An artificial bee colony algorithm with a modified choice function for the traveling salesman problem," Swarm and Evolutionary Computation, 44): 622-635, 2019.

[43] A. C. Parker, J. Pizarro, M. Mlinar, "MAHA: A program for datapath synthesis," presented at the 23rd ACM/IEEE Design Automation Conf., Las Vegas, USA, 29June-2 July, 1986.


Journal of Electrical and Computer Engineering Innovations (JECEI) welcomes letters to the editor for the post-publication discussions and corrections which allows debate post publication on its site, through the Letters to Editor. Letters pertaining to manuscript published in JECEI should be sent to the editorial office of JECEI within three months of either online publication or before printed publication, except for critiques of original research. Following points are to be considering before sending the letters (comments) to the editor.

[1] Letters that include statements of statistics, facts, research, or theories should include appropriate references, although more than three are discouraged.

[2] Letters that are personal attacks on an author rather than thoughtful criticism of the author’s ideas will not be considered for publication.

[3] Letters can be no more than 300 words in length.

[4] Letter writers should include a statement at the beginning of the letter stating that it is being submitted either for publication or not.

[5] Anonymous letters will not be considered.

[6] Letter writers must include their city and state of residence or work.

[7] Letters will be edited for clarity and length.