Fast and Efficient Hardware Implementation of 2D Gabor Filter for a Biologically-Inspired Visual Processing Algorithm

Mohammadi Anbaran, A.; Torkzadeh, P.; Ebrahimpour, R.; Bagheri, N.

doi:10.22061/jecei.2020.7548.404

Document Type : Original Research Paper

Authors

¹ Electrical Engineering Department, Faculty of Engineering, Islamic Azad University, Science and Research Branch, Tehran, Iran.

² Artificial Intelligence Department, Faculty of Computer Engineering, Shahid Rajaee Teacher Training University; Tehran, Iran. School of Cognitive Sciences, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran.

³ Communication Engineering Department, Faculty of Electrical Engineering, Shahid Rajaee Teacher Training University, Tehran, Iran. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran.

https://doi.org/10.22061/jecei.2020.7548.404

Abstract

Background and Objectives: Programmable logic devices, such as Field Programmable Gate Arrays, are well-suited for implementing biologically-inspired visual processing algorithms and among those algorithms is HMAX model. This model mimics the feedforward path of object recognition in the visual cortex.
Methods: HMAX includes several layers and its most computation intensive stage could be the S1 layer which applies 64 2D Gabor filters with various scales and orientations on the input image. A Gabor filter is the product of a Gaussian window and a sinusoid function. Using the separability property in the Gabor filter in the 0° and 90° directions and assuming the isotropic filter in the 45° and 135° directions, a 2D Gabor filter converts to two more efficient 1D filters.
Results: The current paper presents a novel hardware architecture for the S1 layer of the HMAX model, in which a 1D Gabor filter is utilized twice to create a 2D filter. Using the even or odd symmetry properties in the Gabor filter coefficients reduce the required number of multipliers by about 50%. The normalization value in every input image location is also calculated simultaneously. The implementation of this architecture on the Xilinx Virtex-6 family shows a 2.83ms delay for a 128×128 pixel input image that is a 1.86X-speedup relative to the last best implementation.
Conclusion: In this study, a hardware architecture is proposed to realize the S1 layer of the HMAX model. Using the property of separability and symmetry in filter coefficients saves significant resources, especially in DSP48 blocks.

Keywords

20.1001.1.23223952.2021.9.1.10.6

Main Subjects

Image Processing

Open Access

This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit: http://creativecommons.org/licenses/by/4.0/

Publisher’s Note

JECEI Publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Publisher

Shahid Rajaee Teacher Training University

References

[1] D. H. Hubel and T. N. Wiesel, "Receptive fields of single neurones in the cat's striate cortex,” The Journal of physiology, 148(3): 574-591, 1959.

[2] T. Serre, L. Wolf, S. Bileschi, M. Riesenhuber, and T. Poggio, "Robust object recognition with cortex-like mechanisms,” IEEE Trans. on Pattern Analysis & Machine Intelligence, 29(3): 411-426, 2007.

[3] J. Mutch and D. G. Lowe, "Multiclass object recognition with sparse, localized features,” in Proc. Computer Vision and Pattern Recognition conf. (CVPR'06): 11-18, 2006.

[4] S. Rajan, P. Chenniappan, S. Devaraj, and N. Madian, "Facial expression recognition techniques: a comprehensive survey,” IET Image Processing, 13(7): 1031-1040, 2019.

[5] R. Mehrotra, K. R. Namuduri, and N. Ranganathan, "Gabor filter-based edge detection,” Pattern recognition, 25(12): 1479-1494, 1992.

[6] S. Liu, Y. Liu, X. Zhu, Z. Liu, G. Huo, T. Ding, et al., "Gabor Filtering and Adaptive Optimization Neural Network for Iris Double Recognition,” in proc. Chinese Conf. on Biometric Recognition: 441-449, 2018.

[7] G. Amayeh, A. Tavakkoli, and G. Bebis, "Accurate and efficient computation of gabor features in real-time applications,” in proc. Int. Symposium on Visual Computing: 243-252, 2009.

[8] Y. Liang, L. Lu, Q. Xiao, and S. Yan, "Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 39(4): 857-870, 2020.

[9] A. Sironi, B. Tekin, R. Rigamonti, V. Lepetit, and P. Fua, "Learning separable filters,” IEEE Trans. on Pattern Analysis and Machine Intelligence, 37(1): 94-106, 2014.

[10] J. Khosravi, M. Shams Esfandabadi, and R. Ebrahimpour, "Image Registration Based on Sum of Square Difference Cost Function," Journal of Electrical and Computer Engineering Innovations, 6(2): 263-271, 2018.

[11] V. Areekul, U. Watchareeruetai, and S. Tantaratana, "Fast separable gabor filter for fingerprint enhancement," in proc. Int. Conf. on Biometric Authentication: 403-409, 2004.

[12] W.-M. Pang, K.-S. Choi, and J. Qin, "Fast Gabor texture feature extraction with separable filters using GPU," Journal of Real-Time Image Processing, 1(12): 5-13, 2016.

[13] G. Orchard, J. G. Martin, R. J. Vogelstein, and R. Etienne-Cummings, "Fast neuromimetic object recognition using FPGA outperforms GPU implementations," IEEE trans. on neural networks and learning systems, 24(8): 1239-1252, 2013.

[14] A. Al Maashri, M. Cotter, N. Chandramoorthy, M. DeBole, C.-L. Yu, V. Narayanan, et al., "Hardware Acceleration for Neuromorphic Vision Algorithms," Journal of Signal Processing Systems, 70(2): 163-175, 2013.

[15] S. Moini, B. Alizadeh, M. Emad, and R. Ebrahimpour, "A resource-limited hardware accelerator for convolutional neural networks in embedded vision applications," IEEE Trans. on Circuits and Systems II: Express Briefs, 64(10): 1217-1221, 2017.

[16] F. Abdi, P. Amiri, and M. H. Refan, "Low Computational Complexity and High Computational Speed in Leading DCD ERLS Algorithm," Journal of Electrical and Computer Engineering Innovations, 7(1): 19-26, 2019.

[17] S. Chikkerur and T. Poggio, "Approximations in the hmax model," Computer Science and Artificial Intelligence Laboratory, Tech. Rep. MIT-CSAIL-TR-2011-021, 2011.

[18] L. Fei-Fei, R. Fergus, and P. Perona, "Learning generative visual models from few training examples: An incremental bayesian approach tested on 101 object categories," Computer vision and Image understanding, 106(1): 59-70, 2007.

[19] M. DeBole, Y. Xiao, C.-L. Yu, A. Al Maashri, M. Cotter, C. Chakrabarti, et al., "FPGA-accelerator system for computing biologically inspired feature extraction models," in proc. 45th Asilomar Conference on Signals, Systems and Computers (ASILOMAR): 751-755, 2011.

[20] G. D. Licciardo, C. Cappetta, and L. Di Benedetto, "Design of a Gabor Filter HW Accelerator for Applications in Medical Imaging," IEEE Trans. on Components, Packaging and Manufacturing Technology, 8(7): 1187-1194, 2018.

LETTERS TO EDITOR

Journal of Electrical and Computer Engineering Innovations (JECEI) welcomes letters to the editor for the post-publication discussions and corrections which allows debate post publication on its site, through the Letters to Editor. Letters pertaining to manuscript published in JECEI should be sent to the editorial office of JECEI within three months of either online publication or before printed publication, except for critiques of original research. Following points are to be considering before sending the letters (comments) to the editor.

[1] Letters that include statements of statistics, facts, research, or theories should include appropriate references, although more than three are discouraged.

[2] Letters that are personal attacks on an author rather than thoughtful criticism of the author’s ideas will not be considered for publication.

[3] Letters can be no more than 300 words in length.

[4] Letter writers should include a statement at the beginning of the letter stating that it is being submitted either for publication or not.

[5] Anonymous letters will not be considered.

[6] Letter writers must include their city and state of residence or work.

[7] Letters will be edited for clarity and length.

Name *

Email Address *

Affiliation *

Comments *

Security Code *

Journal of Electrical and Computer Engineering Innovations (JECEI)

Fast and Efficient Hardware Implementation of 2D Gabor Filter for a Biologically-Inspired Visual Processing Algorithm

References

References

Send comment about this article

Volume 9, Issue 1
January 2021
Pages 93-102

Fast and Efficient Hardware Implementation of 2D Gabor Filter for a Biologically-Inspired Visual Processing Algorithm

References

References

Send comment about this article

Volume 9, Issue 1January 2021Pages 93-102

Volume 9, Issue 1
January 2021
Pages 93-102