High Speed Delay-Locked Loop for Multiple Clock Phase Generation

Ghanbari, A.; Sadr, A.; Nikoo, M.

doi:10.22061/jecei.2013.1661

Document Type : Original Research Paper

Authors

¹ Graduate School of Electrical Engineering, Qazvin Islamic Azad University (QIAU), Qazvin, Iran

² Department of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, Iran

³ Department of Computer and Electrical Engineering, Islamic Azad University (MIAU)

https://doi.org/10.22061/jecei.2013.1661

Abstract

In this paper, a high speed delay-locked loop (DLL) architecture is presented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which can be triggered by double edges of the input signals. In addition, the blind zone is removed
due to the elimination of reset signal. Therefore, operating frequency of the whole system is improved which can be mentioned as notable advantage of the proposed DLL. To obtain more accurate phases at the output signal, a new delay cell is introduced which is controlled by a single voltage. This control voltage, through equalizing the rise and fall time, regulate duty cycle of output clock. These features along with simplicity and low power consumption qualify the proposed architecture to be widely used in high speed systems. For better realization of the designed circuit’s behavior, simulation results are presented based on TSMC 0.35μm CMOS technology and 3.3-V power supply for a type II filter which demonstrate accuracy and perfect performance of this work.

20.1001.1.23223952.2013.1.1.5.5

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Journal of Electrical and Computer Engineering Innovations (JECEI)

High Speed Delay-Locked Loop for Multiple Clock Phase Generation

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Volume 1, Issue 1 - Serial Number 1
January 2013
Pages 19-27

High Speed Delay-Locked Loop for Multiple Clock Phase Generation

References

References

Send comment about this article

Volume 1, Issue 1 - Serial Number 1January 2013Pages 19-27

Volume 1, Issue 1 - Serial Number 1
January 2013
Pages 19-27