Uncomplicated Dead-time Generation Designed for H-Bridge Drivers by Logic Gates Driving Linear Actuators

Karimi, M.; Dideban, D.

doi:10.22061/jecei.2023.9574.636

Document Type : Original Research Paper

Authors

Department of Electrical Engineering, Faculty of Electrical and Computer Engineering, Kashan University, Kashan, Iran.

https://doi.org/10.22061/jecei.2023.9574.636

Abstract

Background and Objectives: The H-bridge (HB) driver design with high efficiency is one of the most challenging issues in power systems that drive AC/DC loads. HB driver circuit based upon complementary MOSFET type used as a driving system of DC motor, power converters, and battery charger for electrical vehicles. In Driving DC motors, dead-time (DT) generation has been considered a major factor such as preventive power line short-circuit (shoot-through) over high and low-side MOSFETs. In this paper, the HB driver is designed for linear actuators with consideration for the prevention of shoot-through.

Methods: The propagation delay of logic gates are used to postpone the arrival gate drive signal for high/low side MOSFETs resulting in short circuit elimination on the DC source.

Results: As mentioned, logic gates’ propagation delay by their values causes interruption between the high and low-side power switches gate drive signal resulting in shoot-through elimination. Although the existence of DT influences the performance of the rotational speed and output torque of a DC motor by increasing the distortion and pulse interval, Linear actuators due to low-velocity linear motion do not require the PWM control, therefore DT has no substantial effect on driver performance.

Conclusion: Simulation and experimental results validate the method proposed in this paper. According to the specifications of the circuit designed in this paper, for loads that do not need rotational speed control, logic gates with proper propagation delay can be chosen to eliminate short circuits in complementary MOS switches without requiring DT compensation methods.

Keywords

Main Subjects

Electronics

Open Access

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References

[1] K. Mehta “Design implementation of high performance DC drives” in Proc. International Conference on Advances in Computing, Communications and Informatics (ICACCI): 740-745, 2014.

[2] International Rectifier, 55V Single N-Channel HEXFET Power MOSFET in a D2-pack package, IRFZ44ZSPbF datasheet, 2004.

[3] International Rectifier, -55V Single P-Channel HEXFET Power MOSFET in a D2-pack package, IRF5305S datasheet, 2003.

[4] Z. Zhang, F. Wang, D. J. Costinett, L. M. Tolbert, B. J. Blalock, H. Lu, "Dead-time optimization of Sic devices for voltage source converter," in Proc. 2015 IEEE Applied Power Electronics Conference and Exposition (APEC): 1145-1152, 2015.

[5] C. D. Townsend, G. Mirzaeva, G. Goodwin, “Deadtime compensation for model predictive control of power inverters,” IEEE Trans. Power Electron., 32(9): 7325-7337, 2017.

[6] P. Szczesniak, “Challenges and design requirements for industrial applications of AC/AC power converters without DC-link,” Energies, 12(8): 1581, 2019.

[7] J. Zhang, L. Fang, “An accurate approach of dead-time compensation for three-phase DC/AC inverter,” in Proc. the 2009 4th IEEE Conference on Industrial Electronics and Applications: 2929–2934, 2019.

[8] G. Liu, D. Wang, Y. Jin, M. Wang, P. Zhang, “Current-Detection-independent Dead-Time compensation method based on terminal voltage A/D conversion for PWM VSI,” IEEE Trans. Ind. Electron., 64(10): 7689–7699, 2017.

[9] E. S. Kim, U. S. Seong, J. S. Lee, S. H. Hwang, “Compensation of dead time effects in grid-tied single-phase inverter using SOGI,” in Proc. IEEE Applied Power Electronics Conference and Exposition (APEC), 2017.

[10] N. Aizawa, M. Kikuchi, H. Kubota, I. Miki, K. Matsuse, “Dead time effect and its compensation in common-mode voltage elimination of PWM inverter with auxiliary inverter,” in Proc. the 2010 International Power Electronics Conference—ECCE ASIA: 222–227, 2010.

[11] Y. Ji, Y. Yang, J. Zhou, H. Ding, X. Guo, S. Padmanaban, “Control strategies of mitigating dead-time effect on power converters: An overview,” Electronics, 8(2): 196. 2019.

[12] H. Alawieh, L. Riachy, K. Arab Tehrani, K. Azzouz, B. Dakyo, “A new dead-time effect elimination method for H-bridge inverters,” ECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society, 2016.

[13] Z. Ming, M. Zhou, “Impact of zero-voltage notches on outputs of soft switching pulse width modulation converters,” IEEE Trans. Ind. Electron., 58(6): 2345–2354, 2011.

[14] S. Iqbal, A. Xin, M. Jan, M. A. Abdelbaky, H. U. Rehman, S. Salman, M. Aurangzeb, S. Rizvi, N. Shah, “Improvement of power converters performance by an efficient use of dead time compensation technique,” Appl. Sci., 10(9):3121, 2020.

[15] A. Mora, J. Juliet, A. Santander, P. Lezana, “Dead-Time and semiconductor voltage drop compensation for cascaded H-Bridge converters,” IEEE Trans. Ind. Electron., 63(12):7833–7842, 2016.

[16] P. K. Chiu, P. Y. Wang, S. T. Li, C. J. Chen, Y. T. Chen, "A GaN driver IC with novel highly digitally adaptive dead-time control for synchronous rectifier buck converter," in Proc. 2020 IEEE Energy Conversion Congress and Exposition (ECCE): 3788-3792, 2020.

[17] S. Lee, S. Jung, C. Park, C. Rim, G. Cho, "Accurate dead-time control for synchronous buck converter with fast error sensing circuits," IEEE Trans. Circuits Syst. I: Regul. Pap., 60(11): 3080-3089, 2013.

[18] J. Dyer, Z. Zhang, F. Wang, D. Costinett, L. M. Tolbert, B. J. Blalock, “Online condition monitoring based dead-time compensation for high frequency SiC voltage source inverter” in Proc. 2018 IEEE Applied Power Electronics Conference and Exposition (APEC): 1854-1860, 2018.

[19] A. Lewicki, "Dead-Time effect compensation based on additional phase current measurements," IEEE Trans. Ind. Electron. 62(7): 4078-4085, 2015.

[20] B. Bellini, A. Arnaud, S. Rezk, M. Chiossi, "An integrated H-bridge circuit in a HV technology," in Proc. 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS): 331-334, 2016.

[21] E. A. Jones et al., "Characterization of an enhancement-mode 650-V GaN HFET," in Proc. 2015 IEEE Energy Conversion Congress and Exposition(ECCE): 400-407, 2015.

[22] L. Zhang, X. Yuan, J. Zhang, X. Wu, Y. Zhang, C. Wei, "Modeling and implementation of optimal asymmetric variable dead-time setting for SiC MOSFET-Based three-phase two-level inverters," IEEE Trans. Power Electron., 34(12): 11645-11660, 2019.

[23] Y. Zhang, C. Chen, T. Liu, K. Xu, Y. Kang, H. Peng, "A high efficiency model-based adaptive dead-time control method for GaN HEMTs considering nonlinear junction capacitors in triangular current mode operation," IEEE J. Emerging Sel. Top. Power Electron., 8(1): 124-140, 2020.

[24] G. Jianning, D. Naizhe, S. Chonghui, S. Xianrui, X. Zhiwei, “Tri-carrier sinusoidal pulse-width modulation without dead time effects for converters,” IET Power Electronics, 8(10): 1941-1951, 2015.

[25] L. Kang , J. Zhang, H. Zhou, Z. Zhao, X. Duan, “Model predictive current control with fixed switching frequency and dead-time compensation for single-phase PWM rectifier,” Electron., 10(4): 426, 2021.

[26] Z. Zhang, F. Wang, D. J. Costinett, L. M. Tolbert, B. J. Blalock, H. Lu, "Dead-time optimization of SiC devices for voltage source converter," in Proc. 2015 IEEE Applied Power Electronics Conference and Exposition (APEC): 1145-1152, 2015.

[27] Y. Yang, Y. Tang, Y. Li, "Dead-Time elimination method of high frequency inverter with SHEPWM," in Proc. 2019 14th IEEE Conference on Industrial Electronics and Applications (ICIEA): 457-461, 2019.

[28] Nxperia, Quad 2-input NAND Schmitt trigger, HEF4093B, 2015.

[29] Nexperia, Quad 2-input AND gate, HEF4081B, 2022.

[30] Texas Instruments, Quadruple 2-Input positive OR Gate, SN74LS32, 1988.

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Journal of Electrical and Computer Engineering Innovations (JECEI)

Uncomplicated Dead-time Generation Designed for H-Bridge Drivers by Logic Gates Driving Linear Actuators

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Volume 12, Issue 1
January 2024
Pages 69-78

Uncomplicated Dead-time Generation Designed for H-Bridge Drivers by Logic Gates Driving Linear Actuators

References

References

Send comment about this article

Volume 12, Issue 1January 2024Pages 69-78

Volume 12, Issue 1
January 2024
Pages 69-78