Enhancing High-Performance Computing: A Comprehensive Study on Dual-Doped Source/Drain Reconfigurable Field Effect Transistor

Ahangari, Z.

doi:10.22061/jecei.2024.10757.732

Document Type : Original Research Paper

Author

Z. Ahangari

Department of Electronic, Yadegar- e- Imam Khomeini (RAH) Shahr-e-Rey Branch, Islamic Azad University, Tehran, Iran.

https://doi.org/10.22061/jecei.2024.10757.732

Abstract

Background and Objectives: In this study, a reconfigurable field-effect transistor has been developed utilizing a multi-doped source-drain region, enabling operation in both n-mode and p-mode through a simple adjustment of electrode bias. In contrast to traditional reconfigurable transistors that rely on Schottky barrier source/drain with identical Schottky barrier height, the suggested device utilizes a straightforward fabrication process that involves physically multi-doped source and drain. The proposed structure incorporates a bilayer of n+ and p+ in the source and drain regions.
Methods: The device simulator Silvaco (ATLAS) is utilized to conduct the numerical simulations.
Results: The transistor exhibits consistent transfer characteristics in both modes of operation. The influence of key design parameters on device performance has been analyzed. A notable aspect of this transistor is the integration of an XNOR logic gate within a single device, rendering it suitable for high-performance computing circuits. The findings indicate that on-state currents of 142 µA/µm and 57.2 µA/µm, along with on/off current ratio of 8.68×107 and 3.5×107, have been attained for n-mode and p-mode operation, respectively.
Conclusion: A single-transistor XNOR gate design offers potential advantages for future computing circuits due to its simplicity and reduced component count, which could lead to smaller, more energy-efficient, and potentially faster computing systems. This innovation may pave the way for advancements in low-power and high-density electronic devices.

Keywords

Main Subjects

Semiconductor Devices

Open Access

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Journal of Electrical and Computer Engineering Innovations (JECEI)

Enhancing High-Performance Computing: A Comprehensive Study on Dual-Doped Source/Drain Reconfigurable Field Effect Transistor

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Volume 12, Issue 2
July 2024
Pages 475-484

Enhancing High-Performance Computing: A Comprehensive Study on Dual-Doped Source/Drain Reconfigurable Field Effect Transistor

References

References

Send comment about this article

Volume 12, Issue 2July 2024Pages 475-484

Volume 12, Issue 2
July 2024
Pages 475-484