Document Type : Original Research Paper

Author

Department of Electronic, Yadegar- e- Imam Khomeini (RAH) Shahr-e-Rey Branch, Islamic Azad University, Tehran, Iran.

Abstract

Background and Objectives: In this study, a reconfigurable field-effect transistor has been developed utilizing a multi-doped source-drain region, enabling operation in both n-mode and p-mode through a simple adjustment of electrode bias. In contrast to traditional reconfigurable transistors that rely on Schottky barrier source/drain with identical Schottky barrier height, the suggested device utilizes a straightforward fabrication process that involves physically multi-doped source and drain. The proposed structure incorporates a bilayer of n+ and p+ in the source and drain regions.
Methods: The device simulator Silvaco (ATLAS) is utilized to conduct the numerical simulations.
Results: The transistor exhibits consistent transfer characteristics in both modes of operation. The influence of key design parameters on device performance has been analyzed. A notable aspect of this transistor is the integration of an XNOR logic gate within a single device, rendering it suitable for high-performance computing circuits. The findings indicate that on-state currents of 142 µA/µm and 57.2 µA/µm, along with on/off current ratio of 8.68×107 and 3.5×107, have been attained for n-mode and p-mode operation, respectively.
Conclusion: A single-transistor XNOR gate design offers potential advantages for future computing circuits due to its simplicity and reduced component count, which could lead to smaller, more energy-efficient, and potentially faster computing systems. This innovation may pave the way for advancements in low-power and high-density electronic devices.

Keywords

Main Subjects

Open Access

This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit: http://creativecommons.org/licenses/by/4.0/

 

Publisher’s Note

JECEI Publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

 

Publisher

Shahid Rajaee Teacher Training University


LETTERS TO EDITOR

Journal of Electrical and Computer Engineering Innovations (JECEI) welcomes letters to the editor for the post-publication discussions and corrections which allows debate post publication on its site, through the Letters to Editor. Letters pertaining to manuscript published in JECEI should be sent to the editorial office of JECEI within three months of either online publication or before printed publication, except for critiques of original research. Following points are to be considering before sending the letters (comments) to the editor.


[1] Letters that include statements of statistics, facts, research, or theories should include appropriate references, although more than three are discouraged.

[2] Letters that are personal attacks on an author rather than thoughtful criticism of the author’s ideas will not be considered for publication.

[3] Letters can be no more than 300 words in length.

[4] Letter writers should include a statement at the beginning of the letter stating that it is being submitted either for publication or not.

[5] Anonymous letters will not be considered.

[6] Letter writers must include their city and state of residence or work.

[7] Letters will be edited for clarity and length.

CAPTCHA Image