Document Type : Original Research Paper

Authors

Department of Electrical Engineering, Sari Branch, Islamic Azad University, Sari, Iran.

Abstract

Background and Objectives: The background of this research is the significance of current conveyors as essential building blocks in current-mode circuits. The objective is to design and simulate a second generation current conveyor (CCII) in a 180-nm CMOS process, aiming to achieve low impedance, accurate voltage copying, and high DC voltage gain.
Methods: The proposed CCII design utilizes a flipped voltage follower (FVF) to provide low impedance. A novel operational transconductance amplifier (OTA) is introduced to accurately copy the voltage within the circuit. This OTA employs a positive feedback technique to increase its output resistance, thereby enhancing DC voltage gain and reducing input impedance. The performance of the presented CCII is evaluated through simulations in a 180-nm CMOS technology using Cadence software.
Results: The simulation results show the successful operation of the CCII circuit. Key performance metrics include voltage and current tracking errors of 0.3% and 0.1%, respectively, and a bandwidth of 1.4 GHz.
Conclusion: The research concludes that a new OTA and CCII have been successfully simulated in a 180-nm CMOS process. The proposed CCII design, based on FVF and a novel OTA with positive feedback, achieves improved DC voltage gain without compromising other specifications like power consumption, UGBW, and stability. The tracking errors in the proposed method are lower compared to existing approaches.

Keywords

Main Subjects

Open Access

This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit: http://creativecommons.org/licenses/by/4.0/

 

Publisher’s Note

JECEI Publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

 

Publisher

Shahid Rajaee Teacher Training University


LETTERS TO EDITOR

Journal of Electrical and Computer Engineering Innovations (JECEI) welcomes letters to the editor for the post-publication discussions and corrections which allows debate post publication on its site, through the Letters to Editor. Letters pertaining to manuscript published in JECEI should be sent to the editorial office of JECEI within three months of either online publication or before printed publication, except for critiques of original research. Following points are to be considering before sending the letters (comments) to the editor.


[1] Letters that include statements of statistics, facts, research, or theories should include appropriate references, although more than three are discouraged.

[2] Letters that are personal attacks on an author rather than thoughtful criticism of the author’s ideas will not be considered for publication.

[3] Letters can be no more than 300 words in length.

[4] Letter writers should include a statement at the beginning of the letter stating that it is being submitted either for publication or not.

[5] Anonymous letters will not be considered.

[6] Letter writers must include their city and state of residence or work.

[7] Letters will be edited for clarity and length.

CAPTCHA Image