1. High Speed Delay-Locked Loop for Multiple Clock Phase Generation

A. Ghanbari; A. Sadr; M. Nikoo

Volume 1, Issue 1 , Winter and Spring 2013, , Pages 19-27

http://dx.doi.org/10.22061/jecei.2013.17

Abstract
  In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input ...  Read More