S. Yousefian Langroudi; R. Niaraki Asli
Abstract
Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops ...
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Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In this paper we combined these two generally separate addressed issues to reach a new low power high reliability flip-flop (LP-HRFF). LP-HRFF operates over 1GHz clock frequency and structured based on an appropriate combination of dual interlocked storage cell, level converting techniques and clock signal controlled gates. The extensive simulations exhibit LP-HRFF has 0% single event upset rate against single transient events occurred on inputs and internal nodes and show the improvement of power consumption up to 42.8% and power delay product up to 24.6% when compared with its counterparts. Furthermore, the simulation results approve the robustness and efficiency of the proposed flip-flop against process variations.
S. Taghipour; R. Niaraki Asli
Abstract
Due to the expected increase of defects in circuits based on deep submicron technologies, reliability has become an important design criterion. Although different approaches have been developed to estimate reliability in digital circuits and some measuring concepts have been separately presented to reveal ...
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Due to the expected increase of defects in circuits based on deep submicron technologies, reliability has become an important design criterion. Although different approaches have been developed to estimate reliability in digital circuits and some measuring concepts have been separately presented to reveal the quality of analog circuit reliability in the literature, there is a gap to estimate reliability when circuit includes analog and digital structures. In this paper, we propose a new classification method using Monte Carlo analysis to calculate the reliability of analog circuits and show its efficacy when it is used for a combination of analog and digital circuits. Our method is based on signal reliability concepts and measures the probability of passing correct or faulty values. Furthermore, we compare our reliability measurements with the reliability definitions come from other failure mechanisms in sub-micron technologies. Simulation results show the reliability measurement presented here which provides key information for reliability improvement and monitoring.
