S. Yousefian Langroudi; R. Niaraki Asli
Abstract
Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops ...
Read More
Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In this paper we combined these two generally separate addressed issues to reach a new low power high reliability flip-flop (LP-HRFF). LP-HRFF operates over 1GHz clock frequency and structured based on an appropriate combination of dual interlocked storage cell, level converting techniques and clock signal controlled gates. The extensive simulations exhibit LP-HRFF has 0% single event upset rate against single transient events occurred on inputs and internal nodes and show the improvement of power consumption up to 42.8% and power delay product up to 24.6% when compared with its counterparts. Furthermore, the simulation results approve the robustness and efficiency of the proposed flip-flop against process variations.
