Document Type : Original Research Paper

Authors

• S. M. Mousavi Monazah ¹
• N. Shiri ²
• M. Rafiee ²
• A. Sadeghi ³

¹ Nano Opto-Electronics Research Center, Electrical Engineering Department, Shiraz University of Technology, Shiraz, Iran.

² Department of Electrical Engineering, Shi.C., Islamic Azad University, Shiraz, Iran.

³ Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago, IL.

Abstract

Background and Objectives: In modern digital design, ternary logic gives simplicity and efficiency by reducing connectivity and chip area. This paper presents a new ternary decoder with only two ternary inverters and one binary NOR gate. One of the inverters is used simultaneously as a negative ternary inverter (NTI), and a positive ternary inverter (PTI) to attain circuit area reduction. Also, using the binary NOR instead of the ternary NOR eliminates don’t care states (middle voltage mode). The proposed decoder is implemented with complementary metal-oxide-semiconductor (CMOS), double pass logic (DPL), gate diffusion input (GDI), and pass transistor logic (PTL). In the proposed ternary decoder, the four mentioned technologies show an appropriate power delay product (PDP) and a smaller occupied area compared to the literature.
Methods: In this paper, all simulations are performed using the 90 nm model, BSIM4 (level 54) version 4.4 by the HSPICE tool. The CMOS, DPL, PTL, and GDI techniques are used in the presented ternary decoder, and the results are extracted. The decoder shows good functionality compared to the previous research when implemented by these four circuits, but the best performance in terms of PDP results is from the CMOS.
Results: The CMOS-based ternary decoder has only 10 transistors and shows the best results, its power consumption, and propagation delay are 25 μW and 0.07 ns, respectively. Besides, the number of transistors is reduced by 16.66% while it has 2 times increase in speed compared to the best decoders in previous research. The proposed high-speed and low-complexity decoder can be used in full adders (FAs) and digital signal processors (DSPs).
Conclusion: Due to the application and advantage of ternary logic over binary, a ternary decoder with CMOS technique is designed that has fewer elements, a smaller area, and high speed compared to the existing ternary decoders. This new decoder includes only two ternary inverters and one binary NOR gate one of the inverters is used as a negative ternary inverter (NTI), and a positive ternary inverter (PTI), simultaneously. Also, the use of binary NOR gate eliminates don’t care states and reduces the circuit area.

Keywords

• Ternary decode
• CMOS
• High-speed
• Don’t care
• Low-power

Main Subjects

• VLSI

Open Access

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Shahid Rajaee Teacher Training University