1. A Novel Low-Power FPGA-based 1-1 MASH ΔΣ Time-to-Digital Converter Employing one Counter for both Stages

A. Mouri Zadeh Khaki; E. Farshidi; K. Ansari Asl

Volume 7, Issue 2 , Summer and Autumn 2019, , Pages 173-182


  Background and Objectives: Beside acceptable performance, power consumption and chip area are important issues in embedded systems that should be taken into consideration. Methods: In this paper, a novel continuous-time 1-1 MASH ∆∑ Time-to-digital converter (TDC) is presented. Since the proposed ...  Read More