Analogue Integrated Circuits
F. Shakibaee; A. Bijari; S.H. Zahiri
Abstract
Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). So, different structures have been proposed to improve their performance. Power, delay, offset, and noise are the important factors that have significantly affect ...
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Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). So, different structures have been proposed to improve their performance. Power, delay, offset, and noise are the important factors that have significantly affect the comparator’s performance. In low power applications, power consumption and delay are the critical concerns that should be minimized to obtain better performance. In this work, a low-power and high-speed comparator has been proposed, which is suitable for applications operating at a low power supply.Methods: Based on the conventional structure of the comparator, some modifications are implemented to achieve better performance in terms of power consumption and delay. Additionally, the proposed structure gives great performance when the difference of inputs is very small. To verify the proposed structure, it is designed and simulated in a 0.18 μm CMOS technology with a power supply of 1 V and sampling frequency of 2 MHz.Results: To draw a fair comparison, the conventional and proposed structure is simulated in equal circumstance. The size of transistors is designed with appropriate W/L ratios to achieve appropriate performance. The proposed structure not only reduces the power consumption by 44%, but also it decreases the delay by 9.1%. The power consumption of the proposed structure is around 0.12 µw. The total occupied area by the proposed structure is approximately 127.44 µm2.Conclusion: In this paper, we presented a delay analysis for the proposed dynamic comparator. Also, based on theoretical analyses, a new dynamic comparator consumes less power and operates faster compared with the conventional structure. The simulation results verify the theoretical analysis.
S. Mahdavi
Abstract
A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneously ...
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A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper. The main purposes of the proposed idea are to achieve high-resolution and high-speed SAR ADC simultaneously as well. It is noteworthy that, exerting the suggested method the total capacitance and the ratio of the MSB and LSB capacitor are decreased, as a result, the speed and accuracy of the ADC are increased reliably. Therefore, applying the proposed idea, it is reliable that to attain a 12-bit resolution ADC at 76MS/s sampling rate. Furthermore, the power consumption of the proposed ADC is 694µW with the power supply of 1.8 volts correspondingly. The proposed post-layout SAR ADC structure is simulated in all process corner condition and different temperatures of -50℃ to +50℃, and performed using the HSPICE BSIM3 model of a 0.18µm CMOS technology.
