Analogue Integrated Circuits
S. M. Anisheh; M. Khoshnoud; M. Radmehr
Abstract
Background and Objectives: A Time-to-Digital Converter (TDC) is a fundamental electronic component that converts time intervals into digital representations. It plays a critical role in high-precision applications such as particle physics experiments, time-of-flight measurements, and the processing of ...
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Background and Objectives: A Time-to-Digital Converter (TDC) is a fundamental electronic component that converts time intervals into digital representations. It plays a critical role in high-precision applications such as particle physics experiments, time-of-flight measurements, and the processing of high-frequency signals in communication systems. This paper presents a comprehensive study on the design and simulation of two innovative low-power TDC architectures.Methods: The approach introduces a novel low-power D Flip-Flop (D-FF) circuit using transmission gates (TG) and CMOS inverters to reduce power consumption while maintaining high performance. Specialized low-power delay cells are proposed for Flash TDC implementation. Detailed simulations were conducted using Cadence software with a 0.18 μm CMOS fabrication process at a supply voltage of 1.8 V.Results: The results demonstrate significant improvements in power efficiency and performance metrics, indicating the potential of the proposed TDC designs for future applications requiring precise temporal measurements. The Figure of Merit (FOM) values of the two proposed structures are 0.033 and 0.020, respectively.Conclusion: Power consumption in TDCs is a critical factor, as it directly influences the overall efficiency of electronic systems. Reducing power consumption can lead to decreased energy use, improved thermal management, and an extended lifespan for devices. Conversely, higher power consumption can generate excessive heat, which can negatively impact the system's performance and reliability. Thus, it is vital to strike an optimal balance between accuracy and power consumption in TDCs to enhance the longevity of electronic devices. This paper presents the design of delay cell circuits and a D-FF using a 0.18 µm CMOS process with a 1.8 V supply voltage. The power consumption of the proposed delay cells has been minimized through the application of the body bias technique. The performance of the delay cell has been evaluated in flash TDC circuits, and the results demonstrate the effective performance of the proposed structures.
Analogue Integrated Circuits
S. M. Anisheh; E. Tavassoli; M. Radmehr
Abstract
Background and Objectives: The background of this research is the significance of current conveyors as essential building blocks in current-mode circuits. The objective is to design and simulate a second generation current conveyor (CCII) in a 180-nm CMOS process, aiming to achieve low impedance, accurate ...
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Background and Objectives: The background of this research is the significance of current conveyors as essential building blocks in current-mode circuits. The objective is to design and simulate a second generation current conveyor (CCII) in a 180-nm CMOS process, aiming to achieve low impedance, accurate voltage copying, and high DC voltage gain.Methods: The proposed CCII design utilizes a flipped voltage follower (FVF) to provide low impedance. A novel operational transconductance amplifier (OTA) is introduced to accurately copy the voltage within the circuit. This OTA employs a positive feedback technique to increase its output resistance, thereby enhancing DC voltage gain and reducing input impedance. The performance of the presented CCII is evaluated through simulations in a 180-nm CMOS technology using Cadence software.Results: The simulation results show the successful operation of the CCII circuit. Key performance metrics include voltage and current tracking errors of 0.3% and 0.1%, respectively, and a bandwidth of 1.4 GHz.Conclusion: The research concludes that a new OTA and CCII have been successfully simulated in a 180-nm CMOS process. The proposed CCII design, based on FVF and a novel OTA with positive feedback, achieves improved DC voltage gain without compromising other specifications like power consumption, UGBW, and stability. The tracking errors in the proposed method are lower compared to existing approaches.
Analogue Integrated Circuits
A. Yaseri; M. H. Maghami; M. Radmehr
Abstract
Background and Objectives: In recent years, the electronics industry has experienced rapid expansion, leading to increased concerns surrounding the expenses associated with designing and sizing integrated circuits. The reliability of these circuits has emerged as a critical factor influencing the success ...
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Background and Objectives: In recent years, the electronics industry has experienced rapid expansion, leading to increased concerns surrounding the expenses associated with designing and sizing integrated circuits. The reliability of these circuits has emerged as a critical factor influencing the success of production. Consequently, the necessity for optimization algorithms to enhance circuit yield has become increasingly important. This article introduces an enhanced approach for optimizing analog circuits through the utilization of a Multi-Objective Evolutionary Algorithm based on Decomposition (MOEA/D) and includes a thorough evaluation. The main goal of this methodology is to improve both the speed and precision of yield calculations.Methods: The proposed approach includes generating initial designs with desired characteristics in the critical analysis phase. Following this, designs that exceed a predefined yield threshold are replaced with the initial population that has lower yield values, generated using the classical MOEA/D algorithm. This replacement process results in notable improvements in yield efficiency and computational speed compared to alternative Monte Carlo-based methods.Results: To validate the effectiveness of the presented approach, some circuit simulations were conducted on a two-stage class-AB Op-Amp in 180 nm CMOS technology. With a high yield value of 99.72%, the approach demonstrates its ability to provide a high-speed and high-accuracy computational solution using only one evolutionary algorithm. Additionally, the observation that modifying the initial population can improve the convergence speed and yield value further enhances the efficiency of the technique. These findings, backed by the simulation results, validate the efficiency and effectiveness of the proposed approach in optimizing the performance of the Op-Amp circuit.Conclusion: This paper presents an enhanced approach for analog circuit optimization using MOEA/D. By incorporating critical analysis, it generates initial designs with desired characteristics, improving yield calculation efficiency. Designs exceeding a preset yield threshold are replaced with lower yield ones from the initial population, resulting in enhanced computational speed and accuracy compared to other Monte Carlo-based methods. Simulation results for a two-stage class-AB Op-Amp in 180 nm CMOS technology show a yield of 99.72%, highlighting the method's effectiveness in achieving high speed and accuracy with a single evolutionary algorithm.
