Analogue Integrated Circuits
S. M. Anisheh; E. Tavassoli; M. Radmehr
Abstract
Background and Objectives: The background of this research is the significance of current conveyors as essential building blocks in current-mode circuits. The objective is to design and simulate a second generation current conveyor (CCII) in a 180-nm CMOS process, aiming to achieve low impedance, accurate ...
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Background and Objectives: The background of this research is the significance of current conveyors as essential building blocks in current-mode circuits. The objective is to design and simulate a second generation current conveyor (CCII) in a 180-nm CMOS process, aiming to achieve low impedance, accurate voltage copying, and high DC voltage gain.Methods: The proposed CCII design utilizes a flipped voltage follower (FVF) to provide low impedance. A novel operational transconductance amplifier (OTA) is introduced to accurately copy the voltage within the circuit. This OTA employs a positive feedback technique to increase its output resistance, thereby enhancing DC voltage gain and reducing input impedance. The performance of the presented CCII is evaluated through simulations in a 180-nm CMOS technology using Cadence software.Results: The simulation results show the successful operation of the CCII circuit. Key performance metrics include voltage and current tracking errors of 0.3% and 0.1%, respectively, and a bandwidth of 1.4 GHz.Conclusion: The research concludes that a new OTA and CCII have been successfully simulated in a 180-nm CMOS process. The proposed CCII design, based on FVF and a novel OTA with positive feedback, achieves improved DC voltage gain without compromising other specifications like power consumption, UGBW, and stability. The tracking errors in the proposed method are lower compared to existing approaches.
Analogue Integrated Circuits
A. Yaseri; M. H. Maghami; M. Radmehr
Abstract
Background and Objectives: In recent years, the electronics industry has experienced rapid expansion, leading to increased concerns surrounding the expenses associated with designing and sizing integrated circuits. The reliability of these circuits has emerged as a critical factor influencing the success ...
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Background and Objectives: In recent years, the electronics industry has experienced rapid expansion, leading to increased concerns surrounding the expenses associated with designing and sizing integrated circuits. The reliability of these circuits has emerged as a critical factor influencing the success of production. Consequently, the necessity for optimization algorithms to enhance circuit yield has become increasingly important. This article introduces an enhanced approach for optimizing analog circuits through the utilization of a Multi-Objective Evolutionary Algorithm based on Decomposition (MOEA/D) and includes a thorough evaluation. The main goal of this methodology is to improve both the speed and precision of yield calculations.Methods: The proposed approach includes generating initial designs with desired characteristics in the critical analysis phase. Following this, designs that exceed a predefined yield threshold are replaced with the initial population that has lower yield values, generated using the classical MOEA/D algorithm. This replacement process results in notable improvements in yield efficiency and computational speed compared to alternative Monte Carlo-based methods.Results: To validate the effectiveness of the presented approach, some circuit simulations were conducted on a two-stage class-AB Op-Amp in 180 nm CMOS technology. With a high yield value of 99.72%, the approach demonstrates its ability to provide a high-speed and high-accuracy computational solution using only one evolutionary algorithm. Additionally, the observation that modifying the initial population can improve the convergence speed and yield value further enhances the efficiency of the technique. These findings, backed by the simulation results, validate the efficiency and effectiveness of the proposed approach in optimizing the performance of the Op-Amp circuit.Conclusion: This paper presents an enhanced approach for analog circuit optimization using MOEA/D. By incorporating critical analysis, it generates initial designs with desired characteristics, improving yield calculation efficiency. Designs exceeding a preset yield threshold are replaced with lower yield ones from the initial population, resulting in enhanced computational speed and accuracy compared to other Monte Carlo-based methods. Simulation results for a two-stage class-AB Op-Amp in 180 nm CMOS technology show a yield of 99.72%, highlighting the method's effectiveness in achieving high speed and accuracy with a single evolutionary algorithm.
Analogue Integrated Circuits
A. Bijari; M. A. Mallaki
Abstract
Background and Objectives: In wireless communications, receivers play an essential role. Among receiver architectures, the direct-conversion receiver (DCR) architecture has been selected due to its high level of integration and low cost. However, it suffers from DC offset due to self-mixing, I/Q imbalance, ...
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Background and Objectives: In wireless communications, receivers play an essential role. Among receiver architectures, the direct-conversion receiver (DCR) architecture has been selected due to its high level of integration and low cost. However, it suffers from DC offset due to self-mixing, I/Q imbalance, and flicker noise.Methods: This paper presents a new LNA-mixer with variable conversion gain (VG-LM) for wireless local area network (WLAN) applications. A low noise transconductance amplifier (LNTA) is used as the transconductance stage in the Gilbert cell mixer. The wide variable conversion gain range is achieved by the change in LNTA’s transconductance and transconductance of the mixer switching transistors.Results: The proposed LNA-mixer is designed and simulated using 0.18µm CMOS technology in Cadence Spectre RF. The post-layout simulations exhibit the proposed circuit operates at 2.4 GHz with a bandwidth of 10 MHz. In addition, the conversion gain is changed from -3.9 dB to 23.9 dB with the variation of the controlled DC voltage from 0.5 to 1.8. At the high gain, the double-sideband noise figure (DSB-NF) is less than 3.7 dB, and its third-order intermodulation point (IIP3) is -9 dBm. The power consumption is 22 mW from the supply voltage of 1.8 V. The circuit occupies 743 µm×775 µm of core chip area.Conclusion: Using the proposed circuit, the RF front end receiver does not need the low noise amplifier (LNA) and variable gain amplifier (VGA).
Analogue Integrated Circuits
F. Shakibaee; A. Bijari; S.H. Zahiri
Abstract
Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). So, different structures have been proposed to improve their performance. Power, delay, offset, and noise are the important factors that have significantly affect ...
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Background and Objectives: Comparators play a critical role in the analog to digital converters (ADCs) and digital to analog converters (DACs). So, different structures have been proposed to improve their performance. Power, delay, offset, and noise are the important factors that have significantly affect the comparator’s performance. In low power applications, power consumption and delay are the critical concerns that should be minimized to obtain better performance. In this work, a low-power and high-speed comparator has been proposed, which is suitable for applications operating at a low power supply.Methods: Based on the conventional structure of the comparator, some modifications are implemented to achieve better performance in terms of power consumption and delay. Additionally, the proposed structure gives great performance when the difference of inputs is very small. To verify the proposed structure, it is designed and simulated in a 0.18 μm CMOS technology with a power supply of 1 V and sampling frequency of 2 MHz.Results: To draw a fair comparison, the conventional and proposed structure is simulated in equal circumstance. The size of transistors is designed with appropriate W/L ratios to achieve appropriate performance. The proposed structure not only reduces the power consumption by 44%, but also it decreases the delay by 9.1%. The power consumption of the proposed structure is around 0.12 µw. The total occupied area by the proposed structure is approximately 127.44 µm2.Conclusion: In this paper, we presented a delay analysis for the proposed dynamic comparator. Also, based on theoretical analyses, a new dynamic comparator consumes less power and operates faster compared with the conventional structure. The simulation results verify the theoretical analysis.
