Electronics
E. Shafigh Fard; M. A. Jabraeil Jamali; M. Masdari; K. Majidzadeh
Abstract
Background and Objectives: A network on Chip (NoC) is a scalable communication framework that supports several cores. In some cases, while designing a customized Network-on-Chip, the communication needs across IP cores are often uneven, resulting in imbalanced loads on the input ports of a router. The ...
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Background and Objectives: A network on Chip (NoC) is a scalable communication framework that supports several cores. In some cases, while designing a customized Network-on-Chip, the communication needs across IP cores are often uneven, resulting in imbalanced loads on the input ports of a router. The arbitration unit plays a crucial role in the design of the NoC micro-router architecture as it substantially influences the performance, chip occupancy, and power consumption of the NoC. Methods: This article presents a router arbitration architecture that utilizes a mix of variable priority arbitration and round-robin methods. The arbitration process evaluates other channels' requests using the Round Robin index within this architectural framework. A novel approach was suggested to integrate a network router unit onto a single chip, offering several benefits compared to earlier methods. The most significant advantage is its variable priority feature, which allows inputs to be assigned different priority levels regardless of the design circuit. The system is meant to prioritize fairness across all requests by sequentially executing them. The second and primary benefit of the developed circuit is its ability to retain the previously assigned virtual channel ID. This feature preserves the provided virtual channel ID and reduces the time required to verify the requested virtual channels in the subsequent cycle.Results: The evaluation process occurs after the flit has been requested to quit the virtual channel and the availability of the corresponding virtual channel has been verified. The simulation findings demonstrate that the RR-SFVP arbitration unit's design is 12.1% more compact in space than the standard RR approach, offering a promising solution for space-constrained designs. It exhibits 4.3% lower power consumption, a significant improvement in energy efficiency, and 55.1% reduced critical path time, enhancing the system's overall performance. Conclusion: The RR-SFVP technique incorporates all favorable elements in the design of the arbitration unit circuit, such as variable priority and equitable arbitration. Its clear benefits make a strong case for its superiority in the field.
Electronics
A. Ebadiyan; A. Shokri; M. Amirmazlaghani; N. Darestani Farahani
Abstract
Background and Objectives: Semiconductor junction-based radioisotope detectors are commonly used in radioisotope batteries due to their small size and excellent performance. This study aims to design a betavoltaic battery based on a metal-porous semiconductor Schottky structure, comprising an N-type ...
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Background and Objectives: Semiconductor junction-based radioisotope detectors are commonly used in radioisotope batteries due to their small size and excellent performance. This study aims to design a betavoltaic battery based on a metal-porous semiconductor Schottky structure, comprising an N-type zinc oxide (ZnO) semiconductor and platinum (Pt) metal. Methods: we utilized the TCAD-SILVACO 3D simulator to simulate the device, and a C-Interpreter code was applied to simulate the beta particle source, which was an electron beam with an average energy equivalent to 63Ni beta particles. The short circuit current, open-circuit voltage, fill factor (FF), and efficiency of the designed structure were calculated through simulation. Additionally, we discussed the theoretical justification based on the energy band structure. Results: The energy conversion efficiency of the proposed structure was calculated to be 11.37% when bulk ZnO was utilized in the Schottky junction. However, by creating pores and increasing the effective junction area, a conversion efficiency of 35.5% was achieved. The proposed structure exhibited a short-circuit current, open-circuit voltage, and fill factor (FF) of 37.5 nA, 1.237 V, and 76.5%, respectively.Conclusion: This study explored a betavoltaic device with a porous structure based on a Schottky junction between Pt and ZnO semiconductor. The creation of pores increased the contact surface area and effectively trapped beta beams, resulting in improved performance metrics such as efficiency, short circuit current, and open-circuit voltage.
Electronics
Z. Ahangari
Abstract
Background and Objectives: In this study, a reconfigurable field-effect transistor has been developed utilizing a multi-doped source-drain region, enabling operation in both n-mode and p-mode through a simple adjustment of electrode bias. In contrast to traditional reconfigurable transistors that rely ...
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Background and Objectives: In this study, a reconfigurable field-effect transistor has been developed utilizing a multi-doped source-drain region, enabling operation in both n-mode and p-mode through a simple adjustment of electrode bias. In contrast to traditional reconfigurable transistors that rely on Schottky barrier source/drain with identical Schottky barrier height, the suggested device utilizes a straightforward fabrication process that involves physically multi-doped source and drain. The proposed structure incorporates a bilayer of n+ and p+ in the source and drain regions.Methods: The device simulator Silvaco (ATLAS) is utilized to conduct the numerical simulations.Results: The transistor exhibits consistent transfer characteristics in both modes of operation. The influence of key design parameters on device performance has been analyzed. A notable aspect of this transistor is the integration of an XNOR logic gate within a single device, rendering it suitable for high-performance computing circuits. The findings indicate that on-state currents of 142 µA/µm and 57.2 µA/µm, along with on/off current ratio of 8.68×107 and 3.5×107, have been attained for n-mode and p-mode operation, respectively.Conclusion: A single-transistor XNOR gate design offers potential advantages for future computing circuits due to its simplicity and reduced component count, which could lead to smaller, more energy-efficient, and potentially faster computing systems. This innovation may pave the way for advancements in low-power and high-density electronic devices.
Electronics
M. Karimi; D. Dideban
Abstract
Background and Objectives: The H-bridge (HB) driver design with high efficiency is one of the most challenging issues in power systems that drive AC/DC loads. HB driver circuit based upon complementary MOSFET type used as a driving system of DC motor, power converters, and battery charger for electrical ...
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Background and Objectives: The H-bridge (HB) driver design with high efficiency is one of the most challenging issues in power systems that drive AC/DC loads. HB driver circuit based upon complementary MOSFET type used as a driving system of DC motor, power converters, and battery charger for electrical vehicles. In Driving DC motors, dead-time (DT) generation has been considered a major factor such as preventive power line short-circuit (shoot-through) over high and low-side MOSFETs. In this paper, the HB driver is designed for linear actuators with consideration for the prevention of shoot-through.Methods: The propagation delay of logic gates are used to postpone the arrival gate drive signal for high/low side MOSFETs resulting in short circuit elimination on the DC source. Results: As mentioned, logic gates’ propagation delay by their values causes interruption between the high and low-side power switches gate drive signal resulting in shoot-through elimination. Although the existence of DT influences the performance of the rotational speed and output torque of a DC motor by increasing the distortion and pulse interval, Linear actuators due to low-velocity linear motion do not require the PWM control, therefore DT has no substantial effect on driver performance. Conclusion: Simulation and experimental results validate the method proposed in this paper. According to the specifications of the circuit designed in this paper, for loads that do not need rotational speed control, logic gates with proper propagation delay can be chosen to eliminate short circuits in complementary MOS switches without requiring DT compensation methods.
Electronics
G. Asadi Ghiasvand; M. Zare; M. Mahdavi
Abstract
Background and Objectives: Quantum-dot Cellular Automata technology is a new method for digital circuits and systems designs. This method can be attractive for researchers due to its special features such as power consumption, high calculation speed and small dimensions. Methods: This paper tries to ...
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Background and Objectives: Quantum-dot Cellular Automata technology is a new method for digital circuits and systems designs. This method can be attractive for researchers due to its special features such as power consumption, high calculation speed and small dimensions. Methods: This paper tries to design a three-bits counter with minimum area and delay among the other circuits. As the circuit dimensions are reduced, the area and consequently, the delay are decreased, too. Therefore, this paper tries to design a three-bits counter with minimum dimensions and delay. The proposed counter contains 96 cells and is designed in three layers. It has the least area and delay compared to the priors. Results: The circuit simulation illustrates 0.08 µm2 of area occupation and one clock cycle delay. In comparison with the best previous design, which includes 110 cells, the cells number, area and delay are decreased by 12.72%, 27.27% and 33.33%, respectively. Also, the cost of the circuit has been improved by 54.32%. The power analysis of the design shows 13% reduction in the total energy dissipation of the circuit compared to the best prior work. The circuit reliability versus temperature variations has been simulated and the results represent suitable stability. The fault tolerance of the circuit which is occurred by the displacement faults represents normal operation of the circuit.Conclusion: As the counter is an element which is implemented in several digital systems, its area reduction causes the whole system area to be reduced. Also, the circuit delay has been decreased significantly which means that the circuit can be employed by high speed systems.
Electronics
B. Khosravi Rad; M. Khaje; A. Eslami Majd
Abstract
Background and Objectives: One of the common methods for measuring the contact resistance of graphene sheets is the transfer length or transmission line method (TLM). Apart from the contact resistance, TLM gives the resistance of the channel sheet and the effective transfer length of the measured samples. ...
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Background and Objectives: One of the common methods for measuring the contact resistance of graphene sheets is the transfer length or transmission line method (TLM). Apart from the contact resistance, TLM gives the resistance of the channel sheet and the effective transfer length of the measured samples. Furthermore, the implementation of TLM is simple. To analyze this method, one can use circuit modeling (CM).Methods: An important parameter of TLM is the contact resistance between the metal electrode and the graphene channel. To compare this parameter with other measures, it is normalized by multiplying it by the channel width. In this research, for TLM analysis, all the components of the structure including electrodes, graphene channel, and metal-graphene contact are modeled in a circuit.Results: PSpice and MATLAB are integrated for TLM circuit modeling. The metal electrodes and the graphene channel are modeled based on the values of the resistances measured in the laboratory using the van der Pauw method and the resistances reported in the article in ohms per square. Moreover, the metal-graphene contact resistance is considered based on the values reported in the literature in ohms-micrometers.Conclusion: The modeling results show that, in addition to the effective transfer length, the effective transfer width can be defined on a contact, according to the dimensions of the structure. Therefore, the channel width is a vague characteristic of the TLM measurement, which plays a very important role in measuring contact resistance. Furthermore, the contact resistance and the resistance of the channel sheet are independent of each other and of the distance between the contacts. If defects in the graphene channel are randomly distributed along the channel between the contacts, they do not have a significant impact on the contact resistance, while they increase the resistance of the graphene sheet provided that they do not disrupt the channel. Indeed, for a 10% defect (or 90% coverage along the channel), the resistance of the sheet increases by 16%. In addition, by using this modeling, parameters such as the distribution of the contact current, the sources of errors, and their influence in determining the contact resistance and resistance of the channel sheet are investigated.
Electronics
A. Shokri; M. Amirmazlaghani
Abstract
Background and Objectives: The Field-effect Bipolar Junction Transistor (FEBJT) is a device with a bipolar junction transistor (BJT) characteristics except that it is designed with standard CMOS technology. Therefore, it can be implemented in nanometer dimensions without the usual restrictions in fabricating ...
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Background and Objectives: The Field-effect Bipolar Junction Transistor (FEBJT) is a device with a bipolar junction transistor (BJT) characteristics except that it is designed with standard CMOS technology. Therefore, it can be implemented in nanometer dimensions without the usual restrictions in fabricating the nanoscale BJTs. In addition to the advantages that FEBJT has as a bipolar junction transistor in analog circuits, it can also be used to design digital circuits. Here, we have investigated the capability of FEBJT as the base of a new digital family in nanometer scales.Methods: To do this, we have designed and simulated an inverter logic gate based on FEBJT. We have presented this logic gate's static and dynamic assessment criteria and compared these characteristics with other technologies. Also, a three-stage ring oscillator circuit based on FEBJT is designed and presented. A three-dimensional TCAD Mixed-Mode simulator has been used for the simulations.Results: The value of maximum frequency, PDP, dynamic power, and ring frequency are calculated 0.25THz, 38×10-17 J, 94uW, and 85GHz, respectively.Conclusion: The excellent function of the FEBJT-based inverter gate and oscillator demonstrates that this device can be used as the base of new digital circuits and can open a doorway to the nanoscale CMOS digital family.
Electronics
A. Saleh; A.S. Arifin
Abstract
Background and Objectives: In general, traditional salt farmers determine the time to harvest salt by visiting and monitoring their salt ponds. Therefore, to assist salt farmers in determining the right time to harvest salt and determine the quality of the harvested salt, a wireless-based electronic ...
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Background and Objectives: In general, traditional salt farmers determine the time to harvest salt by visiting and monitoring their salt ponds. Therefore, to assist salt farmers in determining the right time to harvest salt and determine the quality of the harvested salt, a wireless-based electronic device is needed that can monitor the salt content and viscosity of the brine.Methods: An electronic device that is made to measure salt content (salinity) with a conductivity sensor and to measure fluid viscosity using a data processing method from sensor readings which is first converted to digital data with a program on the microcontroller. To find out whether the brine is ready to be harvested or not, the data obtained in the form of conductivity and stress are converted into percentages of NaCl and degrees of Baume. Then the data is sent to the ESP8266 wifi module to be stored in a database and displayed on the Web.Results: The results of the data obtained are based on testing in salt ponds for young water but it has been quite a long time the results have approached old water of around 64% and 14o Be. The results of the old water test that had just been moved to the last reservoir were close to harvest time of around 94% and 21o Be. If it has reached 25o Be then it is enough to be moved to the crystallization site. To determine the harvest period based on two parameters, namely the salt content and the viscosity of the liquid is 86-90% and the viscosity of the liquid is 20-24o Be. If you have reached both of these parameters, the salt can be harvested in about 7-10 days to make the water crystallize.Conclusion: Equipment Indicators for determining salt harvest time based on salinity and liquid viscosity using a microcontroller that has been made have been successfully used to determine salt harvest time properly. The salt quality of this indicator tool is the salt content including the K-3 quality or the lowest quality of the 3 existing qualities.
Electronics
E. Rahimi; S. Dorouki
Abstract
Background and Objectives: The displacement of molecules is one of the major fabrication faults in manufacturing molecular electronic devices. In this paper, we profoundly study the effect of displacement on the current-voltage, and conductance-voltage characteristics of the Au-Benzenedithiol-Au single-molecule ...
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Background and Objectives: The displacement of molecules is one of the major fabrication faults in manufacturing molecular electronic devices. In this paper, we profoundly study the effect of displacement on the current-voltage, and conductance-voltage characteristics of the Au-Benzenedithiol-Au single-molecule device.Methods: The ab-initio calculations on the isolated molecules were performed to obtain the basic single-level quantum-dot model parameters. These parameters were then used within the self-consistent field algorithm to calculate the electrical characteristics of the device.Results: The maximum conductance occurs when the molecule is placed exactly in the midpoint of the distance between the two electrodes, where the electrostatic capacitance reaches its minimum. When the molecule deviates from this point, and approaches one electrode, the conductance is decreased, and asymmetric behavior emerges. A molecular rectifier can be manufactured by placing the molecule close to one electrode. Conclusion: Although modern software packages may employ advanced and complicated models including the combination of the density functional theory (DFT) and non-equilibrium Green’s function (NEGF) methods to obtain accurate results, they are demanding in computer memory and time. Moreover, understanding the physical quantities of the systems from large-scale matrices is often difficult. The single-level model is a computationally light method, which provides a profound understanding of the device characteristics since all quantities are presented by numbers.
Electronics
N. Ahmadzadeh Khosroshahi; M. Dehyadegari; F. Razaghian
Abstract
Background and Objectives: This paper introduces a novel low-power and low-delay multi-digit ternary adder in carbon nanotube field effect transistor (CNTFET) technology. Methods: In the proposed design, reducing the power consumption is the main priority. In this multi valued logic design, geometry-dependent ...
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Background and Objectives: This paper introduces a novel low-power and low-delay multi-digit ternary adder in carbon nanotube field effect transistor (CNTFET) technology. Methods: In the proposed design, reducing the power consumption is the main priority. In this multi valued logic design, geometry-dependent threshold voltage of the CNTFET is the design code. At each stage, a half adder is applied to generate the intermediate binary signals called half-sum (HS) and half-carry (HC). For the binary operations, the gate diffusion input (GDI) method is used to significantly reduce the power consumption as in the proposed decoder design. Results: In this work a GDI based sum generator and a low-power encoder are used to calculate the final sum value of each stage. Furthermore, the proposed carry generation/propagation block results in a significant reduction in the overall propagation delay time. The simulation reveals a significant improvement in terms of power consumption (up to 27%), PDP (up to 41%) and FO4 delay (up to 20%).Conclusion: A CNTFET based power and delay efficient multi-digit ternary adder has been presented in this paper. The simulation is performed by the Synopsis HSPICE simulator with Stanford 32 nm CNTFET technology. According to the results, a significant saving in average power consumption is achieved where the power-delay product (PDP) is improved by 41% compared to the best existing design.
Electronics
S. Sadeghi; M. Nayeri; M. Dolatshahi; A. Moftakharzadeh
Abstract
Background and Objectives: In this paper, a novel structure as a Folded-Mirror (FM) Trans-impedance Amplifier (TIA) is designed and introduced for the first time based on the combination of the current-mirror and the folded-cascade topologies. The trans-impedance amplifier stage is the most critical ...
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Background and Objectives: In this paper, a novel structure as a Folded-Mirror (FM) Trans-impedance Amplifier (TIA) is designed and introduced for the first time based on the combination of the current-mirror and the folded-cascade topologies. The trans-impedance amplifier stage is the most critical building block in a receiver system. This novel proposed topology is based on the combination of the current mirror topology and the folded-cascade topology, which is designed using active elements. The idea is to use a current mirror topology at the input node. In the proposed circuit, unlike many other reported designs, the signal current (and not the voltage) is being amplified till it reaches the output node. The proposed TIA benefits from a low input resistance, due to the use of a diode-connected transistor, as part of the current mirror topology, which helps to isolate the dominant input capacitance. So, as a result, the data rate of 5Gbps is obtained by consuming considerably low power. Also, the designed circuit employs only six active elements, which yields a small occupied chip area, while providing 40.6dBΩ of trans-impedance gain, 3.55GHz frequency bandwidth, and 664nArms input-referred noise by consuming only 315µW power using a 1V supply. Results justify the proper performance of the proposed circuit structure as a low-power TIA stage.Methods: The proposed topology is based on the combination of the current mirror topology and the folded-cascade topology. The circuit performance of the proposed folded-mirror TIA is simulated using 90nm CMOS technology parameters in the Hspice software. Furthermore, the Monte-Carlo analysis over the size of widths and lengths of the transistors is performed for 200runs, to analyze the fabrication process.Results: The proposed FM TIA circuit provides 40.6dBΩ trans-impedance gain and 3.55GHz frequency bandwidth, while, consuming only 315µW power using a 1V supply. Besides, as analyzing the quality of the output signal in the receiver circuits for communication applications is vital, the eye-diagram of the proposed FM TIA for a 50µA input signal is opened about 5mV, while, for a 100µA input signal the eye is opened vertically about 10mV. So, the vertical and horizontal opening of the eye is clearly shown. Furthermore, Monte-Carlo analysis over the trans-impedance gain represents a normal distribution with the mean value of 40.6dBΩ and standard deviation of 0.4dBΩ. Also, the value of the input resistance of the FM TIA is equal to 84.4Ω at low frequencies and reaches the value of 75Ω at -3dB frequency. The analysis of the effect of the feedback network on the value of the input resistance demonstrates the input resistance in the absence of the feedback network reaches up to 1.4MΩ, which yields the importance of the existence of the feedback network to obtain a broadband system.Conclusion: In this paper, a trans-impedance amplifier based on a combination of the current-mirror topology and the folded-cascade topology is presented, which amplifies the current signal and converts it to the voltage at the output node. Due to the existence of a diode-connected transistor at the input node, the input resistance of the TIA is comparatively small. Furthermore, four out of six transistors are PMOS transistors, which represent less thermal noise in comparison with NMOS transistors. Also, the proposed Folded-Mirror topology occupies a relatively small area on-chip, due to the fact that no passive element is used in the feedforward network. Results using 90nm CMOS technology parameters show 40.6dBΩ trans-impedance gain, 3.55GHz frequency bandwidth, 664nArms input-referred noise, and only 315µW power dissipation using a 1volt supply, which indicates the proper performance of the proposed circuit as a low-power building block.
Electronics
S. Rahmati; E. Farshidi; J. Ganji
Abstract
Background and Objectives: In recent decades, due to the effect of the short channel, the use of CMOS transistors in the nanoscale has become a major concern. One option to deal with this issue is the use of nano-transistors.Methods: Using nano-transistors and multi-valued logic (MVL) can reduce the ...
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Background and Objectives: In recent decades, due to the effect of the short channel, the use of CMOS transistors in the nanoscale has become a major concern. One option to deal with this issue is the use of nano-transistors.Methods: Using nano-transistors and multi-valued logic (MVL) can reduce the level of chips and connections and have a direct impact on power consumption. The present study reports the design of a new method of Multiplexers (MUXs) based on quaternary logic and transistors of carbon nanotubes (CNTFET) and having a new look at the layout and use of MUXs.Results:The use of special rotary functions and unary operators in Quaternary logic in the design of MUXs reduced the number of CNTFETs from 27% to 54%. Also, the use of MUXs in the Adder structure resulted in a 54% reduction in Power Delay Product (PDP) and a 17.5% to 85.6% reduction in CNTFET counts.Conclusion: The simulated results display a significant improvement in the fabrication of Adders, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits were evaluated under various operating conditions. The results show the stability of the proposed circuits.
Electronics
Z. Kordrostami; S. Hamedi; F. Khalifeh
Abstract
Background and Objectives: High electron mobility transistors (HEMTs) are designed so that they are able to work at higher frequencies than conventional transistors and this has made them an attractive topic of research.Methods: Two developed designs of InGaAs/InAlAs high electron mobility transistors ...
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Background and Objectives: High electron mobility transistors (HEMTs) are designed so that they are able to work at higher frequencies than conventional transistors and this has made them an attractive topic of research.Methods: Two developed designs of InGaAs/InAlAs high electron mobility transistors have been studied. The proposed laterally contacted HEMTs satisfy the desired high frequency characteristics and are good candidates for high frequency applications. Two kinds of HEMTs have been designed and simulated: single-gate laterally contacted HEMT (SGLC-HEMT) and doublegate laterally contacted HEMT (DGLC-HEMT).Results: The proposed SGLC-HEMT exhibits 111 GHz current-gain cut-off frequency. By using double-gate design, the current-gain cut-off frequency has been increased to 256 GHz. The simulation results show that the maximum oscillation frequency for the proposed SGLC and DGLC HEMTs, are 410 GHz and 768 GHz, respectively. The maximum value of transconductance (gm) for SGLC-HEMT is obtained 620 mS/mm while it is 1130 mS/mm for DGLC-HEMT.Conclusion: In order to increase the fT and fmax, instead of decreasing the gate length which is a restricted solution because of short channel effects, a very efficient structure was proposed. The designed HEMT benefits from laterally source and drain contacts. The results showed superior performance of the laterally contacted HEMTs compared to top contacted ones. The best frequency response was obtained for DGLC-HEMT. The proposed DG-HEMT design could improve the current-gain cut-off frequency and maximum oscillation frequency to 256 GHz and 768 GHz, respectively. The comparison of the performance of the DGLC-HEMT with SGLC-HEMT and with previously reported double gate HEMTs, verified the significant improvements in DC and AC characteristics of the HEMTs caused by the proposed design.
Electronics
A. Mouri Zadeh Khaki; E. Farshidi; K. Ansari Asl
Abstract
Background and Objectives: Beside acceptable performance, power consumption and chip area are important issues in embedded systems that should be taken into consideration.Methods: In this paper, a novel continuous-time 1-1 MASH ∆∑ Time-to-digital converter (TDC) is presented. Since the proposed ...
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Background and Objectives: Beside acceptable performance, power consumption and chip area are important issues in embedded systems that should be taken into consideration.Methods: In this paper, a novel continuous-time 1-1 MASH ∆∑ Time-to-digital converter (TDC) is presented. Since the proposed design utilizes 12-bit quantizer based on Gated Switched-Ring Oscillator (GSRO) for both stages, it has been implemented all-digitally. By using a novel structure, only one multi-bit counter is employed for both stages, therefore the required hardware for implementation of this work is much less than conventional TDCs. As a result, complexity, chip area and power consumption would decrease considerably.Results: We implemented the proposed design prototype on an Altera Stratix IV FPGA board. Measured results demonstrate that although this work uses less complex architecture in comparison with previous works, it provides appropriate performance such as 60.7 dB SNR within 8 MHz signal bandwidth at 400 MHz sampling rate while consuming 2.79 mW.Conclusion: Experimental results reveals suitability of the proposed TDC to be incorporated in fast and accurate applications such as ADPLLs and high-resolution photoacoustic tomography. Also, by adjusting the proposed novel structure with more stages higher order of noise-shaping can be attained to enhance SNR and time-resolution further.
Electronics
F. Abdi; P. Amiri; M.H. Refan
Abstract
Background and Objectives: Adaptive algorithm adjusts the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor.Methods: Vedic mathematics ...
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Background and Objectives: Adaptive algorithm adjusts the system coefficients based on the measured data. This paper presents a dichotomous coordinate descent method to reduce the computational complexity and to improve the tracking ability based on the variable forgetting factor.Methods: Vedic mathematics is used to implement the multiplier and the divider operations in the VFF equations. The linear exponentially weighted recursive least squares as the main algorithm is implemented in many applications such as the adaptive controller, the system identification, active noise cancellation techniques, and etc. The DCD method calculates the inverse matrix in the ERLS algorithm and decreases the resources used in the field-programmable gate array, also the designer can use the cheaper FPGA board to implement the adaptive algorithm because the method doesn't need lots of resources.Results: The proposed method is implemented with ISE software on the Spartan 6 Xilinx board. The proposed algorithm calculates the multiplication result with less than 15ns time and reduces the used FPGA resources to lower than 20% as compared with the classic RLS.Conclusion: The proposed method decreases the area and increases the computation speed. Also, it leads to implementing complex algorithms with simple structures and high technology.
Electronics
M. Karbalaei; D. Dideban; N. Moezi
Abstract
Background and Objectives: In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated.Methods: The dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor is a Silicon-channel TFET with ...
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Background and Objectives: In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated.Methods: The dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor is a Silicon-channel TFET with two isolated metal gates (main gate and auxiliary gate) and a source pocket in the channel close to the source-channel junction to increase the carrier tunneling rate.Results: For further enhancement in the tunneling rate, source doping near the source-channel junction, i.e., underneath the auxiliary gate is heavily doped to create more band bending in energy band diagram. Retrograde doping in the channel along with auxiliary gate over the source region also improve device subthreshold swing and leakage current. Based on our simulation results, excellent electrical characteristics with ION/IOFF ratio > 109, point subthreshold swing (SS) of 6 mV/dec and high gm/ID ratio at room temperature shows that this tunneling FET can be a promising device for low power applicationsConclusion: In order to increase the ON-current in this device, we utilized several methods including incorporation of high-K material in top oxide, source pocket in channel and a thin auxiliary gate with high workfunction over the source region. Incorporating auxiliary gate over the source also caused a barrier formation in the energy band diagram profile of this device which it leds electron concentration in the channel, subthreshold swing and OFF-current to be reduced.
Electronics
P. Halvaee; M.S. Beigi
Abstract
Background and Objectives: In this work, porous nanoparticles of ferrite cobalt were prepared by dissolving CoCl2.6H2O and FeCl3 in ethylene glycol in a hydrothermal process. Using ethylene glycol instead of DI water as a solvent would cause to provide porous structure of ferrite cobalt. Methods: In ...
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Background and Objectives: In this work, porous nanoparticles of ferrite cobalt were prepared by dissolving CoCl2.6H2O and FeCl3 in ethylene glycol in a hydrothermal process. Using ethylene glycol instead of DI water as a solvent would cause to provide porous structure of ferrite cobalt. Methods: In the present paper, 0.05 ml of colloidal fluid of fabricated nanostructure was injected on interdigitated electrodes (IDE) on a printed circuit board (PCB) substrate by a drop casting process. Morphological and structural characterizations of structure were investigated by X-ray diffraction and scanning electron microscopy and the obtained results of analyses show the porous nanostructure of the material. Results: Sensor's performance in detection of gas vapors was evaluated in different temperatures which has the best response (20.38% for 100ppm methanol vapors) for methanol vapors at room temperature. performance of sensor in selection of methanol vapors, chemical stability and repeatability of that, makes it useful to profit it in different fields and industries. Conclusion: Porous nanoparticles of CoFe2O4 were prepared by a hydrothermal process. By benefiting of XRD analysis and SEM images, porosity of nanostructure was approved. Response of sensor in different temperatures was measured. At room temperature, it has the best response of 21.38% for 100 ppm methanol vapors. Room temperature working of sensor causes reducing in power consumption and decreasing risks of working in high temperatures. This sensor has a good selectivity to methanol vapors in presence of ethanol, acetone, methane and LPG vapors. Repeatability and chemical stability of sensor in long times of working were approved.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
J. Khosravi; Mohammad Shams Esfand Abadi; R. Ebrahimpour
Abstract
Background and Objectives: There are numerous applications for image registration (IR). The main purpose of the IR is to find a map between two different situation images. In this way, the main objective is to find this map to reconstruct the target image as optimum as possible. Methods: Needless to ...
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Background and Objectives: There are numerous applications for image registration (IR). The main purpose of the IR is to find a map between two different situation images. In this way, the main objective is to find this map to reconstruct the target image as optimum as possible. Methods: Needless to say, the IR task is an optimization problem. As the optimization method, although the evolutionary ones are sometimes more effective in escaping the local minima, their speed is not emulated the mathematical ones at all. In this paper, we employed a mathematical framework based on the Newton method. This framework is suitable for any efficient cost function. Yet we used the sum of square difference (SSD). We also provided an effective strategy in order to avoid sticking in the local minima. Results: The proposed newton method with SSD as a cost function expresses more decent speed and accuracy in comparison to Gradient descent and genetic algorithms methods based on presented criteria. By considering SSD as the model cost function, the proposed method is able to introduce, respectively, accurate and fast registration method which could be exploited by the relevant applications. Simulation results indicate the effectiveness of the proposed model. Conclusion: The proposed innovative method based on the Newton optimization technique on separate cost functions is able to outperform regular Gradient descent and genetic algorithms. The presented framework is not based on any specific cost function, so any innovative cost functions could be effectively employed by our approach. Whether the objective is to reach accurate or fast results, the proposed method could be investigated accordingly.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
S. Ranjbaran; A. Roudbari; S. Ebadollahi
Abstract
Background and Objectives: Using field calibration methods without precision laboratory equipment, systematic faults of inertial sensors can be reduced and measurement accuracy can be increased. Methods: In this paper, a simple and fast method called improved least squares is used to find calibration ...
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Background and Objectives: Using field calibration methods without precision laboratory equipment, systematic faults of inertial sensors can be reduced and measurement accuracy can be increased. Methods: In this paper, a simple and fast method called improved least squares is used to find calibration coefficients of an accelerometer including bias, scale factor and non-orthogonality. In this method, this principal is used that the magnitude of acceleration measured by accelerometer in static condition is equal to the magnitude of gravity vector and a cost function is then defined. Also, in gyroscope field calibration, sensor is rotated manually around all three axes separately and then it is put in the static mode. Changes in the angle obtained from gyroscope at each movement are compared with the ones obtained from the calibrated accelerometer. Calibration coefficients including bias and scale factor are obtained using least squares method. Results: Simulation results in MATLAB show that the measurement accuracy of accelerometer after calibration has improved by about 60% and the accuracy of the gyroscope has increased by about 40%. Also, comparison with the other methods proves that the proposed method performs well in the accuracy, speed, time required, and the effect of noise changes. Conclusion: This paper by finding a fast, simple, and low-cost field calibration method to calibrate MEMS accelerometer and gyroscope without using accurate laboratory equipment can help a wide range of industries that use advanced and expensive sensors or use expensive laboratory equipment to calibrate their sensors, to decrease their costs.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
H. Firoozi; M. Imanieh
Volume 6, Issue 1 , January 2018, , Pages 7-13
Abstract
< p>Background and Objectives: In this article, the functionality of solar cells structure based on CuIn1-xGaxSe2 is investigated. This type of solar cell consists of different layers, namely, ZnO (TCO layer), Cd_S (Buffer layer), CIGS (Absorbent layer), and MO (Substrate layer). Two layers, Cd_S ...
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< p>Background and Objectives: In this article, the functionality of solar cells structure based on CuIn1-xGaxSe2 is investigated. This type of solar cell consists of different layers, namely, ZnO (TCO layer), Cd_S (Buffer layer), CIGS (Absorbent layer), and MO (Substrate layer). Two layers, Cd_S and CIGS, form a PN Junction. < p>Methods: CIGS thin film solar cell is simulated using SILVACO software. The absorbent layer doping was originally changed. Later doping was kept constant and P-type layer of InAsP was added. Their effect on cell function was observed and examined. It was observed that after doping some parameters of the solar cell have improved whilst some others have decreased. It was also concluded that examined increase or decrease in the amount of dopant would reduce our efficiencies of solar cell. < p>Results: Added the InAsP layer leads to increased open circuit voltage, short circuit current and the solar cell power, consequently gives the efficiency about 33.2%, which is an acceptable efficiency. < p>Conclusion: It was clear that extreme increase or decrease in the amount of dopant in the absorbent layer can change solar cell parameters, and can improve cell functionality. < p>The amount of dopants can also alter some other solar cell parameters which are not desirable, the added InAsP layer leads to increased open circuit voltage, and short circuit current and the solar cell power, consequently gives the about 33.2%, efficiency which is an acceptable efficiencies.======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
Electronics
M. Feli; F. Parandin
Abstract
Background and Objectives: Solar cell is an electronic device which harvest photovoltaic effect and transform light energy to electricity. An efficient double junction InGaN/CIGS solar cell can be simulated using Silvaco ATLAS software. In this study, a thin CdS top cover layer is used as the anti-reflector ...
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Background and Objectives: Solar cell is an electronic device which harvest photovoltaic effect and transform light energy to electricity. An efficient double junction InGaN/CIGS solar cell can be simulated using Silvaco ATLAS software. In this study, a thin CdS top cover layer is used as the anti-reflector layer. Methods: To reach the current matching condition, changing the thickness of this CdS layer, we can enhance the short-circuit currents of both the top and bottom cells. To gain a desired efficiency, different design parameters, such as the doping concentrations and the thicknesses of the various layers of the cell are optimized. This cell is designed to be used in a real environmental situation. Results: By using the appropriate parameters, and under matching conditions, the efficiency is optimized as well as the filling factor is increased. Considering the proposed structure and the simulation results, an optimum efficiency of 41.87% is achieved and also the obtained fill factor is equal to 75.16%. Conclusion: In this paper, a new structure for an efficient double junction InGaN/CIGS solar cell, was proposed. In our proposed structure, a thin CdS layer is used as the anti-reflector layer. To get a desired efficiency, different design parameters, such as the doping concentrations and the thicknesses of various layers of the cells were optimized. ======================================================================================================Copyrights©2018 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.======================================================================================================
